DS681 Datasheet, PDF (28/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

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Table 25: Output Timing Adjustments for IOB (Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Speed Grade
-4
Units
Differential Standards
LVDS_25
1.50
ns
LVDS_33
0.47
ns
BLVDS_25
0.11
ns
MINI_LVDS_25
1.11
ns
MINI_LVDS_33
0.41
ns
LVPECL_25
Input Only
LVPECL_33
RSDS_25
1.73
ns
RSDS_33
0.64
ns
TMDS_33
0.07
ns
PPDS_25
1.28
ns
PPDS_33
0.88
ns
DIFF_HSTL_I_18
0.43
ns
DIFF_HSTL_II_18
0.41
ns
Table 25: Output Timing Adjustments for IOB (Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Speed Grade
-4
Units
DIFF_HSTL_III_18
0.36
ns
DIFF_HSTL_I
1.01
ns
DIFF_HSTL_III
1.16
ns
DIFF_SSTL18_I
0.49
ns
DIFF_SSTL18_II
0.41
ns
DIFF_SSTL2_I
0.91
ns
DIFF_SSTL2_II
0.11
ns
DIFF_SSTL3_I
1.18
ns
DIFF_SSTL3_II
0.28
ns
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 26 and are based on the operating
conditions set forth in Table 8, Table 11, and Table 13.
2. These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times that
measure when outputs go into a high-impedance state.
Timing Measurement Methodology
When measuring timing parameters at the programmable
I/Os, different signal standards call for different test
conditions. Table 26 lists the conditions to use for each
standard.
The method for measuring Input timing is as follows: A
signal that swings between a Low logic level of V_L and a
High logic level of V_H is applied to the Input under test.
Some standards also require the application of a bias
voltage to the V_REF pins of a given bank to properly set the
input-switching threshold. The measurement point of the
Input signal (V_M) is commonly located halfway between V_L
and V_H.
The Output test setup is shown in Figure 8. A termination
voltage V_T is applied to the termination resistor R_T, the other
end of which is connected to the Output. For each standard,
R_T and V_T generally take on the standard values
recommended for minimizing signal reflections. If the
standard does not ordinarily use terminations (for example,
LVCMOS, LVTTL), then R_T is set to 1 MΩ to indicate an
open connection, and V_T is set to zero. The same
measurement point (V_M) that was used at the Input is also
used at the Output.
V_T (V_REF)
FPGA Output
R_T (R_REF)
V_M (V_MEAS)
C_L (C_REF)
DS312-3_04_102406
Notes:
1. The names shown in parentheses are
used in the IBIS file.
Figure 8: Output Test Setup
28
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DS681 (v1.1) February 3, 2009
Product Specification