DS681 Datasheet, PDF (37/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

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Clock Buffer/Multiplexer Switching Characteristics
Table 32: Clock Distribution Switching Characteristics
Description
Symbol
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1
inputs. Same as BUFGCE enable CE-input
T_GIO
T_GSI
Frequency of signals distributed on global buffers (all sides)
F_BUFG
Notes:
The numbers in this table are based on the operating conditions set forth in Table 8.
Minimum
–
–
0
Maximum
Speed Grade
-4
0.23
0.63
333
Units
ns
ns
MHz
18 x 18 Embedded Multiplier Timing
Table 33: 18 x 18 Embedded Multiplier Timing
Symbol
Description
Combinatorial Delay
T_MULT
Combinational multiplier propagation delay from the A and B inputs to the P outputs,
assuming 18-bit inputs and a 36-bit product (AREG, BREG, and PREG registers
unused)
Clock-to-Output Times
T_{MSCKP_P}
Clock-to-output delay from the active transition of the CLK input to valid data appearing
on the P outputs when using the PREG register^(2,3)
T_{MSCKP_A}
T_{MSCKP_B}
Setup Times
Clock-to-output delay from the active transition of the CLK input to valid data appearing
on the P outputs when using either the AREG or BREG register^(2,4)
T_{MSDCK_P}
Data setup time at the A or B input before the active transition at the CLK when using
only the PREG output register (AREG, BREG registers unused)⁽³⁾
T_{MSDCK_A}
Data setup time at the A input before the active transition at the CLK when using the
AREG input register⁽⁴⁾
T_{MSDCK_B}
Data setup time at the B input before the active transition at the CLK when using the
BREG input register⁽⁴⁾
Hold Times
T_{MSCKD_P}
Data hold time at the A or B input after the active transition at the CLK when using only
the PREG output register (AREG, BREG registers unused)⁽³⁾
T_{MSCKD_A}
Data hold time at the A input after the active transition at the CLK when using the AREG
input register⁽⁴⁾
T_{MSCKD_B}
Data hold time at the B input after the active transition at the CLK when using the BREG
input register⁽⁴⁾
Speed Grade
-4
Min
Max
–
4.88
–
1.30
–
4.97
3.98
–
0.00
–
0.00
–
0.00
–
0.45
–
0.45
–
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS681 (v1.1) February 3, 2009
www.xilinx.com
37
Product Specification