DS681 Datasheet, PDF (36/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

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Table 30: CLB Distributed RAM Switching Characteristics
Symbol
Description
Clock-to-Output Times
T_SHCKO
Time from the active edge at the CLK input to data appearing on the
distributed RAM output
Setup Times
T_DS
Setup time of data at the BX or BY input before the active transition at the CLK
input of the distributed RAM
T_AS
Setup time of the F/G address inputs before the active transition at the CLK
input of the distributed RAM
T_WS
Setup time of the write enable input before the active transition at the CLK
input of the distributed RAM
Hold Times
T_DH
Hold time of the BX and BY data inputs after the active transition at the CLK
input of the distributed RAM
T_AH, T_WH
Hold time of the F/G address inputs or the write enable input after the active
transition at the CLK input of the distributed RAM
Clock Pulse Width
T_WPH, T_WPL
Minimum High or Low pulse width at CLK input
Speed Grade
-4
Min
Max
–
2.01
–0.02
–
0.36
–
0.59
–
0.13
–
0.01
–
1.01
–
Table 31: CLB Shift Register Switching Characteristics
Symbol
Description
Clock-to-Output Times
T_REG
Time from the active edge at the CLK input to data appearing on the shift
register output
Speed Grade
-4
Min
Max
–
4.82
Setup Times
T_SRLDS
Setup time of data at the BX or BY input before the active transition at the CLK
input of the shift register
0.18
–
Hold Times
T_SRLDH
Hold time of the BX or BY data input after the active transition at the CLK input
of the shift register
0.16
–
Clock Pulse Width
T_WPH, T_WPL
Minimum High or Low pulse width at CLK input
1.01
–
Units
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns
ns
ns
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DS681 (v1.1) February 3, 2009
Product Specification