DS681 Datasheet, PDF (4/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

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I/O Capabilities
The XA Spartan-3A FPGA SelectIO interface supports
many popular single-ended and differential standards.
Table 2 shows the number of user I/Os as well as the
number of differential I/O pairs available for each
device/package combination. Some of the user I/Os are
unidirectional input-only pins as indicated in Table 2.
XA Spartan-3A FPGAs support the following single-ended
standards:
• 3.3V low-voltage TTL (LVTTL)
• Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
• 3.3V PCI at 33 MHz
• HSTL I, II, and III at 1.5V and 1.8V, commonly used in
memory applications
• SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
for memory applications
XA Spartan-3A FPGAs support the following differential
standards:
• LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
3.3V
• Bus LVDS I/O at 2.5V
• TMDS I/O at 3.3V
• Differential HSTL and SSTL I/O
• LVPECL inputs at 2.5V or 3.3V
Table 2: Available User I/Os and Differential (Diff) I/O Pairs
Device
XA3S200A
XA3S400A
XA3S700A
XA3S1400A
FTG256
User Diff
195
90
(35)
(50)
195
90
(35)
(50)
-
-
-
-
FGG400
User Diff
-
-
311
142
(63)
(78)
311
142
(63)
(78)
-
-
FGG484
User Diff
-
-
-
-
372
165
(84)
(93)
375
165
(87)
(93)
Notes:
1. The number shown in bold indicates the maximum number of I/O and input-only
pins. The number shown in (italics) indicates the number of input-only pins. The
differential (Diff) input-only pin count includes both differential pairs on input-only
pins and differential pairs on I/O pins within I/O banks that are restricted to
differential inputs.
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DS681 (v1.1) February 3, 2009
Product Specification