DS681 Datasheet, PDF (23/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

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Input Timing Adjustments
Table 22: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the Following
Signal Standard
(IOSTANDARD)
Add the
Adjustment
Below
Speed Grade
-4
Units
Single-Ended Standards
LVTTL
0.62
ns
LVCMOS33
0.54
ns
LVCMOS25
0
ns
LVCMOS18
0.83
ns
LVCMOS15
0.60
ns
LVCMOS12
0.31
ns
PCI33_3
0.45
ns
HSTL_I
0.72
ns
HSTL_III
0.85
ns
HSTL_I_18
0.69
ns
HSTL_II_18
0.83
ns
HSTL_III_18
0.79
ns
SSTL18_I
0.71
ns
SSTL18_II
0.71
ns
SSTL2_I
0.71
ns
SSTL2_II
0.71
ns
SSTL3_I
0.78
ns
SSTL3_II
0.78
ns
Table 22: Input Timing Adjustments by
Convert Input Time from
LVCMOS25 to the Following
Signal Standard
(IOSTANDARD)
Add the
Adjustment
Below
Speed Grade
-4
Differential Standards
LVDS_25
0.79
LVDS_33
0.79
BLVDS_25
0.79
MINI_LVDS_25
0.84
MINI_LVDS_33
0.84
LVPECL_25
0.80
LVPECL_33
0.80
RSDS_25
0.83
RSDS_33
0.83
TMDS_33
0.80
PPDS_25
0.81
PPDS_33
0.81
DIFF_HSTL_I_18
0.80
DIFF_HSTL_II_18
0.98
DIFF_HSTL_III_18
1.05
DIFF_HSTL_I
0.77
DIFF_HSTL_III
1.05
DIFF_SSTL18_I
0.76
DIFF_SSTL18_II
0.76
DIFF_SSTL2_I
0.77
DIFF_SSTL2_II
0.77
DIFF_SSTL3_I
1.06
DIFF_SSTL3_II
1.06
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 26 and are based on the operating
conditions set forth in Table 8, Table 11, and Table 13.
2. These adjustments are used to convert input path times
originally specified for the LVCMOS25 standard to times that
correspond to other signal standards.
DS681 (v1.1) February 3, 2009
www.xilinx.com
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Product Specification