DS681 Datasheet, PDF (42/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

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Table 38: Switching Characteristics for the DFS (Continued)
Speed Grade
Symbol
Lock Time
LOCK_FX^{(2, 3)}
Description
Device
-4
Min Max
Units
The time from deassertion at the DCM’s
Reset input to the rising transition at its
5 MHz < F_CLKIN All
< 15 MHz
–
5
ms
LOCKED output. The DFS asserts LOCKED
when the CLKFX and CLKFX180 signals are
F_CLKIN > 15 MHz
valid. If using both the DLL and the DFS, use
450
μs
–
the longer locking time.
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 37.
2. DFS performance requires the additional logic automatically added by ISE 9.1i and later software revisions.
3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4. Maximum output jitter is characterized within a reasonable noise environment (40 SSOs and 25% CLB switching) on an
XC3S1400A FPGA. Output jitter strongly depends on the environment, including the number of SSOs, the output drive
strength, CLB utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual
maximum output jitter depends on the system application.
5. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
6. Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data
sheet specifies a maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100
MHz. The equivalent CLKFX period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the
maximum jitter is ±[100 ps + 200 ps] = ±300 ps.
Phase Shifter
Table 39: Recommended Operating Conditions for the PS in Variable Phase Mode
Speed Grade
-4
Symbol
Description
Min
Max
Operating Frequency Ranges
PSCLK_FREQ Frequency for the PSCLK input
(F_PSCLK)
Input Pulse Requirements
1
167
PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period
40% 60%
Units
MHz
–
Table 40: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Phase Shifting Range
MAX_STEPS⁽²⁾
FINE_SHIFT_RANGE_MIN
Description
Maximum allowed number of
CLKIN < 60 MHz
DCM_DELAY_STEP steps for a given
CLKIN clock period, where T = CLKIN
CLKIN ≥ 60 MHz
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE,
double the clock effective clock
period.
Minimum guaranteed delay for variable phase shifting
FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting
Phase Shift Amount
±[INTEGER(10 • (T_CLKIN – 3 ns))]
±[INTEGER(15 • (T_CLKIN – 3 ns))]
±[MAX_STEPS •
DCM_DELAY_STEP_MIN]
±[MAX_STEPS •
DCM_DELAY_STEP_MAX]
Units
steps
ns
ns
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 39.
2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
3. The DCM_DELAY_STEP values are provided at the bottom of Table 36.
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DS681 (v1.1) February 3, 2009
Product Specification