DS681 Datasheet, PDF (31/56 Pages) Xilinx, Inc – Fast look-ahead carry logic

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Simultaneously Switching Output Guidelines
This section provides guidelines for the recommended
maximum allowable number of Simultaneous Switching
Outputs (SSOs). These guidelines describe the maximum
number of user I/O pins of a given output signal standard
that should simultaneously switch in the same direction,
while maintaining a safe level of switching noise. Meeting
these guidelines for the stated test conditions ensures that
the FPGA operates free from the adverse effects of ground
and power bounce.
Ground or power bounce occurs when a large number of
outputs simultaneously switch in the same direction. The
output drive transistors all conduct current to a common
voltage rail. Low-to-High transitions conduct to the V_CCO
rail; High-to-Low transitions conduct to the GND rail. The
resulting cumulative current transient induces a voltage
difference across the inductance that exists between the die
pad and the power supply or ground return. The inductance
is associated with bonding wires, the package lead frame,
and any other signal routing inside the package. Other
variables contribute to SSO noise levels, including stray
inductance on the PCB as well as capacitive loading at
receivers. Any SSO-induced voltage consequently affects
internal switching noise margins and ultimately signal
quality.
Table 27 and Table 28 provide the essential SSO
guidelines. For each device/package combination, Table 27
provides the number of equivalent V_CCO/GND pairs. For
each output signal standard and drive strength, Table 28
recommends the maximum number of SSOs, switching in
the same direction, allowed per V_CCO/GND pair within an
I/O bank. The guidelines in Table 28 are categorized by
package style, slew rate, and output drive current.
Furthermore, the number of SSOs is specified by I/O bank.
Generally, the left and right I/O banks (Banks 1 and 3)
support higher output drive current.
Multiply the appropriate numbers from Table 27 and
Table 28 to calculate the maximum number of SSOs
allowed within an I/O bank. Exceeding these SSO
guidelines might result in increased power or ground
bounce, degraded signal integrity, or increased system jitter.
SSO_MAX/IO Bank = Table 27 x Table 28
The recommended maximum SSO values assumes that the
FPGA is soldered on the printed circuit board and that the
board uses sound design practices. The SSO values do not
apply for FPGAs mounted in sockets, due to the lead
inductance introduced by the socket.
Ball grid array packages are recommended for applications
with a large number of simultaneously switching outputs.
Table 27: Equivalent V_CCO/GND Pairs per Bank
Package Style (Pb-free)
Device
FTG256
FGG400
FGG484
XA3S200A
4
–
–
XA3S400A
4
5
–
XA3S700A
–
5
5
XA3S1400A
–
–
6
DS681 (v1.1) February 3, 2009
www.xilinx.com
31
Product Specification