W681307DG Datasheet, PDF (91/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM.

W681307
13.1.4
Auto Gain Control
： The short term cancelled power is estimated with the following arithmetic unit
( ₍ ) _{) PgShortn}
∝
PgShort _{n −1}
+
 ^{Hsout ∗ 2 AGC _ ST _ ATTACK _ TC −16}
 _{− PgShortn−1 ∗ 2} AGC _ ST _ ATTACK
_ TC −16


： The AGC module is operated with the following algorithm
If ( Hsout > PgShort)
then PgShort = Hsout
If PgShort < AGC _ NOISE _ THRESHOLD
then Sg = 1
Else Sg = ^{AGC _ THRESHOLD}
PgShort
If Sg > AGC _ MAX _ SG
then Sg = AGC _ MAX _ SG
： The long term AGC module gain is estimated with the following arithmetic unit
( ₍ ) _{) Sglongn}
∝ Sglong_n−1
+

Sg ∗ 2 ^{AGC _ LG _ ATTACK}
− Sglong_n−1 ∗ 2 ^{AGC _}
_ TC −16
LG _ ATTACK
_
TC −16

If Sglong > Sg
then Sglong = Sg
13.2
The Software Interface of Speech Processor
The following registers are used to configure the echo canceller. All registers may be both read and written by software. The width of
each location will be a byte within the memory map. Some locations may have unused bits which will be returned undefined values on a
read cycle. Information in these bit positions will be discarded on write cycles.
： The registers within the echo cancellation unit may be segmented into two classes Activation Registers and Performance Adjustment
Registers. An overview of each register class and nominal values to program each register is presented.
13.3
Activation Registers
13.3.1
UP_CONFIG
Address
0x14C0
Access Mode Value At Reset Nominal Value
R/W
0x00
0x82
Bit 7
AGC
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RESERVED
Blocked
Blocked
Blocked
Blocked
(for test modes) (for test modes) (for test modes) (for test modes)
- 91 -
Bit 1
Bit 0
AS1_ENA
Blocked
(for test modes)
Publication Release Date: May, 2007
Revision 1.3