W681307DG Datasheet, PDF (26/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM.

W681307
7. MEMORY AND REGISTER MAP
7.1
Program Memory Map
Program area memory is mapped from 0x0000 to 0xFFFF, this can be used by external ROM.
7.2
Data Memory Map
Data memory address
Size
Function
Comment
0x0000 - 0x0FFF
0x1000 - 0x143F
(except for 0x1401 and 0x1420)
0x1440 - 0x144F
0x1450 - 0x145F
0x1460 - 0x1466
0x1467
0x1468 - 0x146F
0x1470 - 0x1474, 0x150C
(0x1475 ~ 0x147F: To Be Defined)
0x1480 - 0x14BF
(0x1487, 0x1497, 0x149D ~ 0x149F,
0x14A7, 0x14AD ~ 0x14AE, 0x14B7,
0x14BD ~ 0x14BF: To Be Defined)
0x14C0 - 0x14FF
(0x14FA~ 0x14FF: To Be Defined)
0x1500 - 0x151F
(0x1516 ~ 0x1517, 0x1519, 0x151B ~
0x151F: To Be Defined)
(4KB)
(1KB)
(16B)
(16B)
(07B)
(01B)
(15B)
(06B)
(52B)
Not allocated
Blocked for test modes (0x1401 and 0x1420 are activation registers)
Support Logic
Interface Logic
Speech interface
Multiplexer to connect 5 PCM channels to 4 DSP channels
Fine tune gain
Processor Interface (AuxOpPort,DiagSel,Diag_CS,Diag_CS3,Multiplier_enable)
Transcoder DSP Registers
(58B)
(24B)
Half Acoustic Echo Canceller Registers
MCU System Register
0x1520 - 0x157F (except for 0x1521)
(96B) Blocked for test modes (0x1521 is TI path selection register)
0x1580 - 0x15BF
0x15C0 - 0x15CF
(0x15C7, 0x15CF: To Be Defined)
(64B)
(14B)
(Reserved)
Acoustic side / Network side Power Measurement
0x15D0 - 0x16FF
(304B) (Reserved)
0x1700 – 0x171F
(0x1705 ~ 0x1707, 0x170D ~ 0x170F,
(11B)
PCM highway
0x1711 ~ 0x171F: To Be Defined)
0x1720 – 0x1728
0x1729 ~ 0x172F: To Be Defined)
(9B)
Master or slave SPI interface
0x1730 ~ 0x173F
(16B) Data Flash SPI interface
0x1740 – 0x175F
(0x174B ~ 0x175F: To Be Defined)
(11B) _{W2S interface}
0x1760 – 0x177B
(0x1764: To Be Defined)
(27B) _{Blocked for test modes}
0x1800 ~ 0x187F
(127) USB control registers
0x1900 ~ 0x1901
(2B)
ISP mode control register
0x5000 - 0x6FFF
(8KB) Reserved for On-chip Expansion
0x7000 - 0x7FFF
(4KB) On chip data RAM
*4
0x8000 - 0xEFFF
(4-28KB) External data RAM programmable selected by CS1
*2
0xF000 - 0xFFFF
(4KB) External data RAM selected by CS2
*3
*1. Specific registers are blocked for test modes of hardware logic functions.
*2. The On-chip RAM is contiguous with CS1, which is used for off chip RAM.CS2 is the same.
*3. CS1 is a programmable address range, CS1 can be programmable range starting at 0x8000 and ending at 0xEFFF, with step 4K. CS2 is the same.
*4. In the event of further on chip RAM being required this can be put in this reserved location, hence on-chip and off chip RAM will remain contiguous.
The address decoding logic in this chip will not decode this area.
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Publication Release Date: May, 2007
Revision 1.3