W681307DG Datasheet, PDF (63/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM.

W681307
10.7.2
10.7.2.1
The Description of PCM Highway Interface Registers
PCM channel format and delay control of 1^st group (PCM B1, PCM B2)
Address
0x1700h
Access Mode
R/W
Value At Reset
0x02
Bit 7
Bit 6
Bit 5
Bit 4
PCMB1_dis Half rate PCMB2_dis RESERVED
Bit 3
Hizen
Half/Full
Bit 2
RESERVED
Bit 1
Data
16/8bits
Bit 0
RESERVED
Data 16/8bits
Hizen Half/Full
PCMB2_dis
Half rate
PCMB1_dis
Set the bit to receive/transmit 16 bits; Reset the bit to receive/transmit 8 bits.
Set the bit to tristate in the end of the bit. Reset the bit to tristate in the falling edge of the end of the
bit.
=1: disabling the B2 channel of the PCM Highway.
=0: enabling the B2 channel of the PCM Highway.
Set the bit for one bit per 2 Bitclk (during data length being 16 bits=>0x1700 [1] =1’b1). Reset the bit
for one bit per 1 Bitclk.
=1: disabling the B1 channel of the PCM Highway.
=0: enabling the B1 channel of the PCM Highway.
10.7.2.2
Address
0x1701h
TX delay1
Access Mode Value At Reset
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TX delay1
Set the values for delaying the transmitted bits of PCM B1 channel after the rising edge of the frame pulse. The resolution is one bitclk in
full date rate and two Bitclk in half data rate.
10.7.2.3
Address
0x1702h
TX delay2
Access Mode
R/W
Value At Reset
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TX delay2
Set the values for delaying the transmitted bits of PCM B2 channel after the tail bit of PCM B1 channel. The resolution is one PCM
Bitclk in full date rate and two Bitclk in half data rate.
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Publication Release Date: May, 2007
Revision 1.3