W681307DG Datasheet, PDF (54/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM.

W681307
9.4.1
Watch Dog Control
Address
0x145A
Access Mode Value At Reset Nominal Value
R/W
0x00
Bit 7
Reserved
Bit 6
WatchDog
ResetEn
Bit 5
Bit 4
Bit 3
Watch Dog Timer [2:0]
Bit 2
WatchDogEn
Bit 1
Bit 0
KeyBounce[1:0]
WatchDogEn
WatchDogTimer [2:0]
WatchDogResetEn
KeyBounce[1:0]
When set, enable the watchdog, which use system clock source 2.
Controls the repetition rate of the watchdog timer 1 second to 8 seconds.
When set, it will reset whole baseband chip.
Key Debounce Period Selection.
The de-bounce period is defined as follows:
All times are +/- 0.5ms
Key-Bounce Period
8 ms
16 ms
24 ms
32 ms
KeyBounce[1:0]
0x00
0x01
0x02
0x03
9.4.2
Address
0x145B
Timer 1ms Control1
Access Mode Value At Reset Nominal Value
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer1msLength[5:0]
Timer1msEn
Timer1ms
Reset
Timer1msLength[5:0]
Timer1msEn
Timer1msReset
1ms timer counter, which controls the repetition rate of the 1ms timer up to 64 ms.
When set to ‘1’, enable 1ms timer to proceed from it’s previous status. When reset to ‘0’, this just pause the
operation but not reset the content.
When reset to ‘0’, reset the 1ms timer. This timer will operate only when this bit remains ‘1’.
9.4.3
Timer Control
Address
0x145C
Access Mode Value At Reset Nominal Value
R/W
0x00
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Reset 1S
counter
Bit 3
Reserved
Bit 2
Reserved
Bit 1
Reset 1mS
counter
Bit 0
Reset 1S timer
1S timer reset
1mS counter reset
1S counter reset
when reset to “0”, reset the 1S timer.
when reset to “0”, reset the 1mS counter, but this bit does not affect the operation of 1ms timer which is
controlled by 0x145B.
when reset to “0”, reset the 1S counter value in 0x145D, but this bit does not affect the operation of 1S timer.
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Publication Release Date: May, 2007
Revision 1.3