W681307DG Datasheet, PDF (27/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM.

W681307
7.3
Register Map
7.3.1
Mixer and Speech Logic Registers Overview
Address Name
Mode
Value At
Reset
Function
0x1401
Mixer_En
R/W
0x00
Enable the mixer block.
0x1420
SPEECH LOGIC_EN
R/W
0x04
Enable the four channels of speech logic interface (which is
not needed by the CODEC).
(0x1000 ~ 0x143F are blocked for test modes except for 0x1401 and 0x1420)
7.3.2
Address
0x1440
0x1441
0x1442
0x1443
0x1444
0x1445
0x1446
0x1447
0x1448
0x1449
0x144A
0x144B
0x144C
0x144D
0x144E
0x144F
Support Logic Registers Overview
Name
ClockEnable
IntrptSource0
IntrptSource1
IntrptEnable0
IntrptEnable1
IntrptPriority0
IntrptPriority1
SounderTone1
SounderTone2
SounderVol1
SounderVol2
PIEZO Function
PIEZO Clock output
IntrptSource2
IntrptEnable2
IntrptPriority2
Mode
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value At
Reset
0x78
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Function
Clock 3, 4 & 5 Enable Bits and Reset 32K logic
Interrupt source register 0
Interrupt source register 1
Interrupt enable register 0
Interrupt enable register 1
Interrupt priority register 0
Interrupt priority register 1
Sounder frequency control register 1
Sounder frequency control register 2
Sounder volume control register 1
Sounder volume control register 2
PIEZO Enable and frequency select
Output the PIEZO driving clock
Interrupt source register 2
Interrupt enable register 2
Interrupt priority register 2
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Publication Release Date: May, 2007
Revision 1.3