W681307DG Datasheet, PDF (134/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM.

16.4
FSM
There have 3 states in the DF_SPI module : IDLE, CMD and DATA.
W681307
Step1. While power on reset, the FSM initial is in the IDLE state.
Step2. After enable the DF_SPI function (write REG 0x1730[7]=1), the FSM start to wait the CPU control to change to CMD state (write
REG 0x1731), then force control logic to shift out the command bytes sequentially to serial data flash.
Step3. After finished shift out the command bytes, the FSM will change to DATA state if the Data_enb (REG 0x1731[4]) is true, or run
back to IDLE state if the Data_enb is false.
Step4. When FSM goes into Data state, the control logic will start to shift out the write out data to serial data flash if DF_RD (REG
0x1731[3]) is false, or shift in the read back data from serial data flash if DF_RD (REG 0x1731[3]) if true.
Step5. After finished shift out/in the data bytes, the FSM will go back to IDLE state, and wait for next transition.
16.5
FIFO/RAM
： ^{The DF_SPI module takes 5 bytes register to write the control command and takes the 256x8 bytes RAM to do the Read/Write access}
FIFO. It supports 2 kinds of memory access method
Type1. FIFO like method:
The CPU always read/write the same address, then the hardware control the memory read/write address, and increase the
read/write point automatically after each read/write. The current write/read point can be read back at REG 0x173E/0x173F.
Type2. Direct access method:
The CPU can read/write any byte of the memory with write the read (REG 0x173F)/write (REG 0x173E) point first.
16.6
Interrupt
The DF_SPI module supports two kinds of interrupt source. One is the TX/RX finish interrupt, occur while TX/RX byte counts (REG
0x173D) is equal to DATA_LEN, the other is middle flag interrupt, occur while TX/RX byte counts (REG 0x173D) is equal to the 16 *
INTR_CNT (REG 0x1733[7:4]). Any other concept, please reference to the description of the registers.
16.7
16.7.1
DF_SPI Register Group
DF_CLK
Address
0x1730
Access Mode Value At Reset Nominal Value
R/W
00
Bit 7
DF_ENB
CLK_REG
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CLK_REG [6:0]
Clock Divider Base to decide the DF_clk clock frequency.
DF_CLK freq. = CPU CLK freq. / (CLK_REG + 1)
EX: CLK_REG [6:0] = 0x01→ DF_CLK freq. = CPU CLK freq. / 2
≧ ^{CLK_REG [6:0] = 0x03 → DF_CLK freq. = CPU CLK freq. / 4}
Note: CLK_REG [6:0] must 1 while DF_CLK active.
Bit 0
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Publication Release Date: May, 2007
Revision 1.3