W681307DG Datasheet, PDF (41/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM.

W681307
Sysclock4En
Sysclock5En
Reset32K
When set, enable system clock 4.
When set, enable system clock 5.
set low to reset the 32KHz clock source.
8.2
Interrupt Control
8.2.1
Overview
The Support and Interface Logic generate internal events, these interrupt events are conditioned by the Interrupt Control logic before it is
issued to the Processor. Figure 8-2 shows the interrupt structure.
8.2.2
Functionality
The Support and Interface Logic generate interrupt events as one-cycle pulses. The Support and Interface Logic generate the following
interrupts:
• Hardware Keypad Scanner Interrupt
• Keypad port input general purpose IO Interrupt
• Timer Interrupt
• Speech Interface Interrupt
• WatchDog Interrupt
The Speech Interface generates the following interrupts: -
• PCM Port Input General Purpose IO Interrupt
Three registers control the generation of interrupts in the MCU chip, the IntrptSource register, the IntrptEnable register and the
IntrptPriority register. Each interrupt has a corresponding bit in the IntrptSource, IntrptEnable and IntrptPriority registers.
• The IntrptSource register is set when an interrupt event occurs and is cleared by Processor write.
• When the Processor writes to IntrptSource, any bits that are set to 1 cause the corresponding bit of IntrptSource to be cleared,
bits set to 0 are not affected.
• An Interrupt is generated when IntrptSource AND IntrptEnable =1 for any of the interrupt sources.
• For each bit; if IntrptPriority =0, the interrupt is issued to INT0, if IntrptPriority =1, the interrupt is issued to INT1.
• The watchdog interrupt is implemented for debug purposes only. The Watchdog must be kicked before attempting to clear its
associated source register.
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Publication Release Date: May, 2007
Revision 1.3