W681307DG Datasheet, PDF (127/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM.

W681307
15. SERIAL PERIPHERAL INTERFACE
15.1
Serial Peripheral Interface – SPI signals
• SCK: Input pin in slave mode; output pin in master mode. Serial Clock from Master. Max clock rate is TBD MHz
(depends on how fast the CPU to read a word of received data).
• /SPI_CS: Input pin in slave mode; output pin in master mode. Low active Chip Select signal from Master.
• MISO: Output pin in slave mode; input pin in master mode. Slave data out to the input of Master.
• MOSI: Input pin in slave mode; output pin in master mode. Master data out to the input of Slave.
If the phase of the clock is zero, i.e. CPHA = 0, data is latched at the rising edge of the clock with CPOL = 0, and at the falling edge of
the clock with CPOL = 1. If CPHA = 1, the polarities are reversed. CPOL = 0 means falling edge, CPOL = 1 rising edge. The
transmission clock edges are the reversed of sampling edges, shown in Figure 15-1. Timing diagram of CPHA = 0 and CPHA = 1 is
shown in Figure 15-2 and Figure 15-3.
Figure 15-1 Sampling edges of different modes
Figure 15-2 Timing diagram of CPHA = 0 ( SS is the pin /SPI_CS)
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Publication Release Date: May, 2007
Revision 1.3