W681307DG Datasheet, PDF (128/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM.

W681307
Figure 15-3 Timing Diagram of CPHA = 1 ( SS is the pin /SPI_CS)
15.1.1
SPI_Control 0
Address
0x1720
Access Mode Value At Reset Nominal Value
R/W
00
Bit 7
Bit 6
SPI_Enable
SPI_Master_Mo
de
Bit 5
Reserved
Bit 4
Reserved
Bit 3
DumpComp
Bit 2
Reserved
Bit 1
CPHA
Bit 0
CPOL
SPI_Enable
Spi_master_mode
CPOL
CPHA
DumBcomp
SPI interface enable. If SPI_ENB=0, the SPI is disabled and pins defined as original functions. Default to 0.
set to 1 in master mode. Default to slave mode
Clock polarity, if CPOL=0, clock is active high; if CPOL=1, clock is active low. Default to 0.
Clock Phase, determined the sampling clock edge of SCLK. Default to 0.
When this bit is on and the received byte is the same as Dumpbyte (0x1724), then no write to RX fifo.
SPI mode 0 = 0x80; SPI mode 1 = 0x82; SPI mode 2 = 0x81; SPI mode 3 = 0x83;
Note: 0x1720[1:0] = ‘10’ is mode 1 in figure 1; 0x1720[1:0] = ‘01’ is mode 2 in figure 1.
15.1.2
SPI_Control 1
Address
0x1721
Access Mode Value At Reset Nominal Value
R/W
00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI_Clock
Reserved
Reserved
RxDepth_intr[3:0]
SPI_Clock
Set master spi clock speed. (Master mode only)
00 1.152MHz
01 576KHz
10 256KHz
11
64KHz
The SPI in slave mode support maximum clock speed is 576K.
Rxdepth_intr An RxINT interrupt event 1723[bit 4] is generated when received byte count reaches Rxdepth_intr[bit 3:0] +1 bytes.
- 128 -
Publication Release Date: May, 2007
Revision 1.3