W681307DG Datasheet, PDF (141/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM.

W681307
17. WINBOND 2-WIRE SERIAL BUS
17.1
Introduction to Winbond 2-Wire Serial bus
Winbond 2-wire serial bus (W2S) is a simple bi-directional 2-wire bus for efficient inter-IC control. This design is for W2S master use
only, and governed by micro controller, typically an 8032. The W2S used in the chip is used to both read/write from/to EEPROM and
control melody device. The W2S master controller equips 35 bytes FIFO performing W2S formatting and de-formatting. The micro
controller can simply fill up the FIFO contents which consists of target device ID, high/low address (depend on the device format); for
reading, just set read enable , for writing, keep writing data to FIFO then set write enable to launch transmission. The W2S master
controller supports up to 3 kinds of page writing, i.e. 8, 16, 32 bytes. The W2S master controller designed to support maximum 32 bytes
per page, and the FIFO depth is calculated as 3 header bytes (one device ID, two address) plus 32 bytes for data. It has various bus speed
configurations to support wide range of EEPROM bus speed.
17.2
17.2.1
The Description of W2S Register
W2S_Enable
Address
0x1740
Access Mode Value At Reset Nominal Value
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
W2S_ENA W2S_Port_Sel RESERVED RESERVED RESERVED RESERVED RESERVED
Bit 0
W2S_HW
_Protection
W2S_ENA: Set this bit will activate W2S bus controller.
W2S_Port_Sel: Pin selection for hardware W2S bus function.
W2S_Port_Sel
Pin name
0
P1.2 : SDA0
P1.3 : SCL0
※¹
P1.3 : SDA1
P1.4 : SCL1
If W2S_HW_Protection is set to 1, the couple of pins set by bit W2S_Port_Sel become tri-state as core power below the operation
voltage (see following table).
※ Micro-C must set W2S_ENA bit before setup Force_Activity (0x1745) register, and the content of W2S Status (0x1746) is valid only
if W2S_ENA bits is set to 1.
W2S_HW_Protection: Set this bit will force W2S bus pins into tri-state output mode, when the CPWR_Det is low activity. Which pins
will be forced to tri-state output is dependent on the W2S_ENA and W2S_Port_Sel bits setting. The forced pins are listed as below when
the bit CPWR_Det is low. That means the core power voltage is below 1.7V. And the hardware W2S bus will into protection mode to
avoid the E2PROM data corruption.
Table 17-1
CPWR_Det
(Read only)
0
1
W2S_HW_Protection
0
1
Don’t care
W2S_ENA
X
Don’t care
Don’t care
W2S_Port_Sel
X
0
1
Don’t care
P1.2
X
V
X
X
P1.3
X
V
V
X
： ^P1.4
X
PS V means this pin is forced to tri-state output mode.
X
V
X
X means this pin state no any change.
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Publication Release Date: May, 2007
Revision 1.3