W681307DG Datasheet, PDF (123/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM.

W681307
ADC_FIFO_OverflowFIFO pointer overflow in the ADC path.
ADC_FIFO_underflowFIFO pointer underflow in the ADC path.
DAC_FIFO_OverflowFIFO pointer overflow in the DAC path.
DAC_FIFO_underflowFIFO pointer underflow in the DAC path.
ADC_SINC_OverflowOverflow indication for ADC SINC filter.
ADC_SINC_UnderflowUnderflow indication for ADC SINC filter.
14.17
BandGap Voltage Adjustment
Address
0x1513
Access Mode Value At Reset Nominal Value
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reserved
Vbgp_trimming[5:0]
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
±
80mV
40mV
20mV
10mV
5mV
Bandgap voltage is default 1V. You can fine tune bandgap voltage follow below formula.
－ When set Vbgp_trimming[5] = 1, BandGap Voltage = 1V 5mV * Vbgp_trimming[4:0]
＋ When set Vbgp_trimming[5] = 0, BandGap Voltage = 1V 5mV * Vbgp_trimming[4:0]
Where Vbgp_trimming [4:0] is a decimal value and ranges from 0 to 31
14.18
Specific Register
Address
0x1514
Access Mode Value At Reset Nominal Value
R/W
0x00
Bit 7
Blocked
(for test modes)
Bit 6
Bit 5
Bit 4
Blocked (for test modes)
Bit 3
Blocked
(for test modes)
Bit 2
Bit 1
Bit 0
Blocked (for test modes)
14.19
Linear Regulator Voltage Controller Register
Address
0x1515
Access Mode Value At Reset Nominal Value
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RESERVED RESERVED RESERVED RESERVED REG_LV[1] REG_LV[0] RESERVED RESERVED
The output voltage of the embedded linear regulator (REG) is correlated to the internal bandgap voltage. Any tolerance and deviation of
the bandgap voltage will cause a deviation of the output voltage of the embedded linear regulator. In order to ease the usage, the
adjustment possibilities of output voltage of the linear regulator have been built in to compensate the bandgap variation in process.
REG_LV[1:0]
REG_LV [1:0]
00
01
10
11
REG Output Voltage
3.0V
3.1V
3.2V
3.3V
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Publication Release Date: May, 2007
Revision 1.3