W681307DG Datasheet, PDF (109/160 Pages) Winbond – USB1.1 CODEC Microprocessor Control Unit with 32KB Mask ROM and 4KB RAM.

W681307
14. SYSTEM FUNCTION
14.1
Power On Reset
The power on reset (POR) block generates a internal reset signal to reset the whole chip after connecting the power supply voltage the
chip. The power on reset circuit responds to the voltage difference applied between AVDD and AGND. Figure 14-1 shows the power
reset circuit.
When AVDD is rising slowly starting from zero to the signal PowerOnResetN will be low until AVDD passed the power-on voltage level
Von. After a delay time (about 37ms for 13.824MHz clock) Reset_out goes high and the actual reset sequence starts. If AVDD does not
pass Von voltage, then the PowerOnResetN stays low, causing the oscillator to run and having most of the digital logic circuits being in
an active reset mode. If AVDD sinks below the power-off voltage level Voff, PowerOnRestN will become low again. The hysteresis
voltage between Von and Voff is need to overcome a “reset oscillation” phenomenon that otherwise might occur if AVDD decrease due
to the activity during the reset sequence.
Figure 144-1 Analog part of the power on Reset function.
14.1.1
CODEC On/Off Scheme
Address
0x1500
Access Mode Value At Reset
R/W
0x00
Bit 7
Bit 6
Bit 5
Bit 4
RESERVED RESERVED RESERVED RESERVED
Bit 3
Bit 2
PeriodSelection
Bit 1
Bit 0
CODECOnOff
Codec on/off _{scheme Enable}
CODECOnOff_scheme_Enable
CODEC On/Off
PeriodSelection
Set “1” to enable hardwired CODEC On/Off scheme.
Set “0” to use independent On/Off control from 0x1509.
Set“1” to turn on CODEC.
Set “0” to turn off CODEC.
Set to select the duration length between CODEC_digital_on/off and
CODEC_analog_on/off.
Bit[3:2]
2’b00
2’b01
2’b10
2’b11
Period
2 mS
4 mS
8 mS
16 mS
- 109 -
Publication Release Date: May, 2007
Revision 1.3