W83977F Datasheet, PDF (82/181 Pages) Winbond – PLUG & PLAY 1.0A COMPLIANT

W83977F/ W83977AF
PRELIMINARY
4.8.1 Set6.Reg0 - Infrared Configure Register 2 (IR_CFG2)
This register controls ASK-IR, MIR, FIR operations.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
IR_CFG2 SHMD_N SHDM_N FIR_CRC MIR_CRC
-
Reset Value
0
0
1
0
0
Bit 2
Bit 1
INV_CRC DIS_CRC
0
0
Bit 0
-
0
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 2:
Bit 1:
Bit 0:
SHMD_N - ASK-IR Modulation Disable
SHMD_N
Modulation Mode
0
IRTX modulate 500K Hz Square Wave
1
Re-rout IRTX
SHDM_N - ASK-IR Demodulation Disable
SHDM_N
Demodulation Mode
0
1
FIR_CRC - FIR (4M bps) CRC Type
FIR_CRC
Demodulation 500K Hz
Re-rout IRRX
CRC Type
0
16-bit CRC
1
32-bit CRC
Note that the 16/32-bit CRC are defined in IrDA 1.1 physical layer.
MIR_CRC - MIR (1.152M/0.576M bps) CRC Type
MIR_CRC
CRC Type
0
1
INV_CRC - Inverting CRC
16-bit CRC
32-bit CRC
When set to 1, the CRC is inversely output in physical layer.
DIS_CRC - Disable CRC
When set to 1, the transmitter does not transmit CRC in physical layer.
Reserved, write 1.
4.8.2 Set6.Reg1 - MIR (1.152M/0.576M bps) Pulse Width
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
MIR_PW
-
-
-
M_PW4 M_PW3
Reset Value
0
0
0
0
1
This 5-bit register sets MIR output pulse width.
Bit 2
M_PW2
0
Bit 1
M_PW1
1
Bit 0
M_PW0
0
M_PW4~0
00000
00001
00010
...
k₁₀
...
11111
MIR Pulse Width (1.152M bps)
0 ns
20.83 ns
41.66 (==20.83*2) ns
...
20.83*k₁₀ ns
...
645 ns
MIR Output Width (0.576M bps)
0 ns
41.66 ns
83.32 (==41.66*2) ns
...
41.66*k₁₀ ns
...
1290 ns
- 70 -
Publication Release Date: March 1998
Revision 0.58