W83977F Datasheet, PDF (74/181 Pages) Winbond – PLUG & PLAY 1.0A COMPLIANT

W83977F/ W83977AF
PRELIMINARY
Bit 4:
Bit 3:
Bit 2:
ALOOP - All Mode Loopback
A write to 1 will enable loopback in all modes.
D_CHSW - DMA TX/RX Channel Swap
If only one DMA channel operates in MIR/FIR mode, then the DMA channel can be
swapped.
D_CHSW
DMA Channel Selected
0
Receiver (Default)
1
Transmitter
A write to 1 will enable output data when ALOOP=1.
DMATHL - DMA Threshold Level
Set DMA threshold level as shown in the following table.
DMATHL
0
1
TX FIFO Threshold
16-Byte
32-Byte
13
13
23
7
RX FIFO Threshold
(16/32-Byte)
4
10
Bit 1:
Bit 0:
DMA_F - DMA Fairness
DMA_F
Function Description
0
DMA request (DREQ) is forced inactive after 10.5us
1
No effect DMA request.
ADV_SL - Advanced Mode Select
A write to 1 selects advanced mode.
4.4.3 Reg3 - Sets Select Register (SSR)
Reading this register returns E0H. Writing a value selects Register Set.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
SSR
Refault Value
SSR7
1
SSR6
1
SSR5
1
SSR4
0
SSR3
0
SSR2
0
Bit 1
SRR1
0
Bit 0
SRR0
0
4.4.4 Reg4 - Advanced IR Control Register 2 (ADCR2)
Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Advanced IR DIS_BACK - PR_DIV1 PR_DIV0 RX_FSZ1 RX_FSZ0 TX_FSZ1 TXFSZ0
Reset Value
0
0
0
0
0
0
0
0
Bit 7:
Bit 6:
Bit 5, 4:
DIS_BACK - Disable Backward Operation
A write to 1 disables backward legacy IR mode. When operate in legacy SIR/ASK-IR
mode, this bit should be set to 1 to avoid backward operation.
Reserved, write 0.
PR_DIV1~0 - Pre-Divisor 1~0.
These bits select pre-divisor for external input clock 24M Hz. The clock goes through the
pre-divisor then input to baud rate divisor of IR.
PR_DIV1~0
00
01
10
11
Pre-divisor
13.0
1.625
6.5
1
Max. Baud Rate
115.2K bps
921.6K bps
230.4K bps
1.5M bps
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Publication Release Date: March 1998
Revision 0.58