W83977F Datasheet, PDF (17/181 Pages) Winbond – PLUG & PLAY 1.0A COMPLIANT

W83977F/ W83977AF
PRELIMINARY
1. PIN DESCRIPTION
Note: Please refer to Section 11.2 DC CHARACTERISTICS for details.
I/O6t - TTL level bi-directional pin with 6 mA source-sink capability
I/O8t - TTL level bi-directional pin with 8 mA source-sink capability
I/O8
- CMOS level bi-directional pin with 8 mA source-sink capability
I/O12t - TTL level bi-directional pin with 12 mA source-sink capability
I/O12 - CMOS level bi-directional pin with 12 mA source-sink capability
I/O16u - CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistor
I/OD16u - CMOS level bi-directional pin open drain output with 16 mA sink capability with internal pull-up resistor
I/O24t - TTL level bi-directional pin with 24 mA source-sink capability
OUT8t - TTL level output pin with 8 mA source-sink capability
OUT12t - TTL level output pin with 12 mA source-sink capability
OD12 - Open-drain output pin with 12 mA sink capability
OD24 - Open-drain output pin with 24 mA sink capability
INt
- TTL level input pin
INc
- CMOS level input pin
INcu - CMOS level input pin with internal pull-up resitor
INcs - CMOS level Schmitt-triggered input pin
INts
- TTL level Schmitt-triggered input pin
INtsu - TTL level Schmitt-triggered input pin with internal pull-up resistor
1.1 Host Interface
SYMBOL
A0−A10
A11-A14
A15
D0−D5
D6−D7
IOR
IOW
AEN
IOCHRDY
PIN
74-84
86-89
91
109-114
116-117
105
106
107
108
MR
118
I/O
IN_t
IN_t
IN_t
I/O_12t
I/O_12t
IN_ts
IN_ts
IN_t
OD₂₄
IN_ts
FUNCTION
System address bus bits 0-10
System address bus bits 11-14
System address bus bit 15
System data bus bits 0-5
System data bus bits 6-7
CPU I/O read signal
CPU I/O write signal
System address bus enable
In EPP Mode, this pin is the IO Channel Ready output to
extend the host read/write cycle.
Master Reset. Active high. MR is low during normal
operations.
Publication Release Date: March 1998
-6-
Revision 0.58