W83977F Datasheet, PDF (59/181 Pages) Winbond – PLUG & PLAY 1.0A COMPLIANT

W83977F/ W83977AF
PRELIMINARY
7 6 54 3 210
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.
TABLE 3-3 FIFO TRIGGER LEVEL
BIT 7
BIT 6
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
0
0
01
0
1
04
1
0
08
1
1
14
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if
UFR bit 0 = 1.
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to
a logical 0 by itself after being set to a logical 1.
Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to
a logical 0 by itself after being set to a logical 1.
Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1
before other bits of UFR are programmed.
3.2.6 Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
Publication Release Date: January 1997
-48 - Revision 0.50