W83977F Datasheet, PDF (110/181 Pages) Winbond – PLUG & PLAY 1.0A COMPLIANT

6.3.2 Register 0Bh (Read/Write)
BIT
7
6
5
NAME
SET
PE
AE
W83977F/ W83977AF
PRELIMINARY
4
3
2
UE Reserved DM
1
12/24
0
DSE
SET
When the SET bit is set, any occurring update cycle is aborted and registers (Register 00h~09h,
Register (40h~48h) may be modified without entering an update cycle. When this bit is cleared, the
update cycle function occurs once per second. This bit is not affected by any other internal functions
or by a RESET.
PE
A "1" on the periodic interrupt enable bit enables the periodic interrupt flag (PF) bit in Register 0Ch to
assert an interrupt.
A "0" on this bit blocks the IRQ output from being driven by a periodic interrupt. This bit can not be
modified by any internal function, but it may be cleared by a RESET.
AE
A "1" on the enable bit of alarm A enables the alarm A flag (AF) bit in Register 0Ch to assert an
interrupt.
A "0" on this bit prohibits alarm A interrupt. The RESET signal clears AE to "0". This bit can not be
modified by any internal function.
UE
A "1" on this bit enables the update-ended flag (UF) bit in register C to assert an interrupt.
A "0" on this bit prohibits update-ended interrupt. The UE bit is cleared by setting the SET bit or by a
RESET.
DM
The data mode bit determines whether time and calendar updates are in binary format or in binary-
coded-decimal (BCD) format.
A "1" on this bit means binary format.
A "0" on this bit means BCD format. This bit can not be modified by a RESET or any internal
function.
24/12
A "1" on this bit selects 24-hour mode for the time-of-day function.
A "0" on this bit selects 12-hour mode. This bit can not be modified by a RESET or any internal
function.
DSE
A "1" on this bit allows two special updates:
• On the last Sunday of April, the time increments from 1:59:59 AM to 3:00:00 AM.
• On the last Sunday of October, the time decrements from 1:59:59 AM to 1:00:00 AM.
A "0" on this bit disables these special updates. DSE can not be changed by any internal operation or
a RESET.
(Note: RTC IRQ is ultimately controlled by Logical Device 4-CR70 and Logical Device 4-CR71. These two registers must be set
properly if RTC IRQ is needed)
- 98 -
Publication Release Date: January 1997
Revision 0.50