W83977F Datasheet, PDF (116/181 Pages) Winbond – PLUG & PLAY 1.0A COMPLIANT

W83977F/ W83977AF
6.7.4 "On-Now" Register 4 (Bank2 Register 4Ch)
PRELIMINARY
BIT
7
6
5
4
3
NAME PSOFDS1 PSOFDS0 INVSMI Reserved MCLKD
2
1
0
KCLKD PWAKI2D PWAKI1D
This register is read only except bits 5, 6 and 7.
PSOFDS1, PSOFDS0
These two bits decide the delay time between panel switch power off event and power supply off.
00 : 0 second.
01 : 5 seconds.
10 : 13 seconds.
11 : 21 seconds.
INVSMI
Logical 1 on this bit, nSMI is active low and goes high-Z when dis-asserted.
Logical 0 on this bit, nSMI is active high and goes high-Z when dis-asserted.
MCLKD (MCLK Detect)
A falling edge transition on MCLK asserts this bit. This bit is cleared by reading this register.
KCLKD (KCLK Detect)
A falling edge transition on KCLK asserts this bit. This bit is cleared by reading this register.
PWAKI2D (PWAKIN2 Detect)
A falling edge transition on PWAKIN2 asserts this bit. This bit is cleared by reading this register.
PWAKI1D (PWAKIN1 Detect)
A falling edge transition on PWAKIN1 asserts this bit. This bit is cleared by reading this register.
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Publication Release Date: January 1997
Revision 0.50