W83977F Datasheet, PDF (153/181 Pages) Winbond – PLUG & PLAY 1.0A COMPLIANT

W83977F/ W83977AF
CRF2 (Default 0x00)
PRELIMINARY
Watching Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to
load the value to Watching Dog Counter and start to count down. If the Bit2 and Bit 1 are set, any
Mouse Interrupt or Keyboard Interrupt happen will also cause to reload the non-zero value to
Watching Dog Counter and count down. Read this register can not access Watching Dog Timer
Time-out value, but can access the current value in Watching Dog Counter.
Bit 7-0 :
= 0x00 Time-out Disable
= 0x01 Time-out occurs after 1 minute
= 0x02 Time-out occurs after 2 minutes
= 0x03 Time-out occurs after 3 minutes
................................................
= 0xFF Time-out occurs after 255 minutes
CRF3 (WDT_CTRL0, Default 0x00)
Watching Dog Timer Control Register #0
Bit 7-4 : Reserved
Bit 3 : When Time-out occurs, Enable or Disable Power LED with 1 Hz and 50% duty cycle output.
= 1 Enable
= 0 Disable
Bit 2 : Mouse interrupt reset Enable or Disable
= 1 Watching Dog Timer is reset upon a Mouse interrupt
= 0 Watching Dog Timer is not affected by Mouse interrupt
Bit 1 : Keyboard interrupt reset Enable or Disable
= 1 Watching Dog Timer is reset upon a Keyboard interrupt
= 0 Watching Dog Timer is not affected by Keyboard interrupt
Bit 0 : Reserved.
CRF4 (WDT_CTRL1, Default 0x00)
Watching Dog Timer Control Register #1
Bit 7-4 : Reserved
Bit 3 : Enable the rising edge of Keyboard Reset(P20) to force Time-out event, R/W*
= 1 Enable
= 0 Disable
Bit 2 : Force Watching Dog Timer Time-out, Write only*
= 1 Force Watching Dog Timer time-out event; this bit is self-clearing.
Bit 1 : Enable Power LED 1Hz rate toggle pulse with 50% duty cycle , R/W
= 1 Enable
= 0 Disable
Bit 0 : Watching Dog Timer Status, R/W
= 1 Watching Dog Timer time-out occurred.
= 0 Watching Dog Timer counting
*Note : 1). Internal logic provides an 1us Debounce Filter to reject the width of P20 pulse less than 1us.
2). The P20 signal that coming from Debounce Filter is ORed with the signal generated by the Force Time-out bit and then
connect to set the Bit 0(Watching Dog Timer Status). The ORed signal is self-clearing.
- 141 -
Publication Release Date: March 1998
Revision 0.58