W83977F Datasheet, PDF (73/181 Pages) Winbond – PLUG & PLAY 1.0A COMPLIANT

W83977F/ W83977AF
PRELIMINARY
4.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)
These two registers of BLL and BHL are baud rate divisor latch in the legacy SIR/ASK-IR mode.
Accessing these registers in Advanced IR mode will cause backward operation, that is, UART will fall
back to legacy SIR mode and clear some register values as shown in the following table.
Set & Register
Set 0.Reg 4
Set 2.Reg 2
Set 4.Reg 3
Advanced Mode
DIS_BACK=^¡Ñ
Bit 7~5
Bit 0, 5, 7
Bit 2, 3
Legacy Mode
DIS_BACK=0
-
Bit 5, 7
-
Note that DIS_BACK=1 (Disable Backward operation) in legacy SIR/ASK-IR mode will not affect any
register which is meaningful in legacy SIR/ASK-IR.
4.3.2 Set1.Reg 2~7
These registers are defined as the same as Set 0 registers.
4.4 Set2 - Interrupt Status or IR FIFO Control Register (ISR/UFR)
These registers are only used in advanced modes.
Address Offset Register Name
Register Description
0
ABLL
Advanced Baud Rate Divisor Latch (Low Byte)
1
ABHL
Advanced Baud Rate Divisor Latch (High Byte)
2
ADCR1
Advanced IR Control Register 1
3
SSR
Sets Select Register
4
ADCR2
Advanced IR Control Register 2
5
Reserved
-
6
TXFDTH
Transmitter FIFO Depth
7
RXFDTH
Receiver FIFO Depth
4.4.1 Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL)
These two registers are the same as legacy IR baud rate divisor latch in SET 1.Reg0~1. In advanced
SIR/ASK-IR mode, user should program these registers to set baud rate. This is to prevent backward
operation from occurring.
4.4.2 Reg2 - Advanced IR Control Register 1 (ADCR1)
Mode
Bit 7 Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Advanced IR BR_OUT - EN_LOUT ALOOP D_CHSW DMATHL
Reset Value
0
0
0
0
0
0
Bit 1
DMA_F
0
Bit 0
ADV_SL
0
Bit 7:
Bit 6:
Bit 5:
BR_OUT - Baud Rate Clock Output
When written to 1, the programmed baud rate clock will be output to DTR pin. This bit is
only used to test baud rate divisor.
Reserved, write 0.
EN_LOUT - Enable Loopback Output
A write to 1 will enable transmitter to output data to IRTX pin when loopback operation.
Internal data can be verified through an output pin by setting this bit.
- 61 -
Publication Release Date: March 1998
Revision 0.58