W83977F Datasheet, PDF (66/181 Pages) Winbond – PLUG & PLAY 1.0A COMPLIANT

Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
W83977F/ W83977AF
PRELIMINARY
Legacy IR Mode:
Not used. A read will return 0.
MIR, FIR, Remote IR:
EDMAI - Enable DMA Interrupt.
A write to 1 will enable DMA interrupt.
Reserved. A read will return 0.
Legacy IR Mode:
EUSRI - Enable USR (IR Status Register) Interrupt
A write to 1 will enable IR status register interrupt.
Advanced SIR/ASK-IR:
EUSRI - Enable USR (IR Status Register) Interrupt
A write to 1 will enable IR status register interrupt.
MIR, FIR, Remote Controller:
EHSRI/ETXURI - Enable USR Interrupt or Enable Transmitter Underrun Interrupt
A write to 1 will enable USR interrupt or enable transmitter underrun interrupt.
ETBREI - Enable TBR (Transmitter Buffer Register) Empty Interrupt
A write to 1 will enable the transmitter buffer register empty interrupt.
ERBRI - Enable RBR (Receiver Buffer Register) Interrupt
A write to 1 will enable receiver buffer register interrupt.
4.2.3 Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR)
4.2.3.1 Interrupt Status Register (Read Only)
Mode
B7
B6
B5
Legacy IR
Advanced
IR
Reset Value
FIFO Enable FIFO Enable
TMR_I
FSF_I
0
0
0
TXTH_I
1
B4
0
DMA_I
0
B3
IID2
HS_I
0
B2
IID1
USR_I/
FEND_I
0
B1
B0
IID0
IP
TXEMP_I RXTH_I
1
0
Legacy IR:
This register reflects the Legacy IR interrupt status, which is encoded by different interrupt sources
into 3 bits.
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4: These two bits are always logical 0.
Bit 3: When not in FIFO mode, this bit is always 0. In FIFO mode, both bit 3 and 2 are set to logical
1 when a time-out interrupt is pending.
Bit 2, 1: These bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has
occurred, this bit will be set to logical 0.
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Publication Release Date: March 1998
Revision 0.58