W83977F Datasheet, PDF (111/181 Pages) Winbond – PLUG & PLAY 1.0A COMPLIANT

6.3.3 Register 0Ch (Read only)
BIT
7
6
5
4
NAME IRQF
PF
AF
UF
W83977F/ W83977AF
PRELIMINARY
3
2
1
0
0
0
0
0
IRQF
The interrupt request flag is set to a "1" if one or more of following cases are true:
PF*PE = "1"
AF*AE = "1"
UF*UE = "1"
(i.e., IRQF = PF*PE + AF*AE + UF*UE)
Any time the IRQF bit is a "1", the IRQ is asserted (provided LD4-CR70 and LD4-CR71 are set
properly). All flags are cleared by reading the register or by a RESET.
PF
The periodic interrupt flag is set to "1" when a rising edge is detected on the selected tap of the
divider chain(RS[3:0] of register A). PF is set to a "1" regardless of the state of PE bit. This bit is
cleared by a RESET or when this register is read.
AF
A "1" on this bit indicates that the current time has reached the alarm time setting (alarm A). A
RESET or a read of this register clears this bit.
UF
The update-ended interrupt flag bit is set after the end of each update cycle. This bit is cleared by a
RESET or when this bit is read.
Bit 3 - Bit 0
These bits are reserved and all read "0".
6.3.4 Register D (Read only)
BIT
7
6
5
4
3
2
1
0
NAME
VRT
0
0
0
0
0
0
0
VRT
The valid RAM and time bit. A "0" appears on this bit when the external battery is removed or at low-
voltage during power-failure situation, indicating the data integrity of the real time clock, "On-Now"
logic, and storage registers is not guaranteed. This bit can only be set by reading this register, and is
not affected by a RESET.
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Publication Release Date:March 1998
Revision 0.58