W83977F Datasheet, PDF (67/181 Pages) Winbond – PLUG & PLAY 1.0A COMPLIANT

W83977F/ W83977AF
TABLE: INTERRUPT CONTROL FUNCTION
PRELIMINARY
ISR
INTERRUPT SET AND FUNCTION
Bit Bit Bit Bit Interrupt Interrupt Type
3 2 1 0 priority
Interrupt Source
Clear Interrupt
0 001
-
0 1 1 0 First
-
IR Receive Status
0 1 0 0 Second RBR Data Ready
1 1 0 0 Second FIFO Data Time-out
0 0 1 0 Third
TBR Empty
** Bit 3 of ISR is enabled when bit 0 of UFR is a logical 1.
No Interrupt pending
1. OER = 1 2. PBER =1
3. NSER = 1 4. SBD = 1
1. RBR data ready
2. FIFO interrupt active level
reached
Data present in RX FIFO for 4
characters period of time since last
access of RX FIFO.
TBR empty
-
Read USR
1. Read RBR
2. Read RBR until FIFO
data under active level
Read RBR
1. Write data into TBR
2. Read ISR (if priority is
third)
Advanced IR:
Bit 7:
TMR_I - Timer Interrupt.
Set to 1 when timer count to logical 0. This bit is valid when: (1) the timer registers are
defined in Set4.Reg0 and Set4.Reg1; (2) EN_TMR(Enable Timer, in Set4.Reg2.Bit0) is
Bit 6:
set to 1; (3) ENTMR_I (Enable Timer Interrupt, in Set0.Reg1.Bit7) is set to 1.
MIR, FIR modes:
FSF_I - Frame Status FIFO Interrupt.
Set to 1 when Frame Status FIFO is equal or larger than the threshold level or Frame
Status FIFO time-out occurs. Cleared to 0 when Frame Status FIFO is below the
Bit 5:
threshold level.
Advanced SIR/ASK-IR, Remote IR modes: Not used.
TXTH_I - Transmitter Threshold Interrupt.
Set to 1 if the TBR (Transmitter Buffer Register) FIFO is below the threshold level.
Bit 4:
Cleared to 0 if the TBR (Transmitter Buffer Register) FIFO is above the threshold level.
MIR, FIR, Remote IR Modes:
DMA_I - DMA Interrupt.
Set to 1 if the DMA controller 8237A sends a TC (Terminal Count) to I/O device which
Bit 3:
might be a Transmitter TC or a Receiver TC. Cleared to 0 when this register is read.
HS_I - Handshake Status Interrupt.
Set to 1 when the Handshake Status Register has a toggle. Cleared to 0 when
Handshake Status Register (HSR) is read. Note that in all IR modes including SIR, ASK-
IR, MIR, FIR, and Remote Control IR, this bit defaults to be inactive unless IR Handshake
Bit 2:
Status Enable (IRHS_EN) is set to 1.
Advanced SIR/ASK-IR modes:
USR_I - IR Status Interrupt.
Set to 1 when overrun error, parity error, stop bit error, or silent byte error detected and
registered in the IR Status Register (USR). Cleared to 0 when USR is read.
MIR, FIR modes:
FEND_I - Frame End Interrupt.
Set to 1 when (1) a frame has a grace end to be detected where the frame signal is
defined in the physical layer of IrDA version 1.1; (2) abort signal or illegal signal has been
detected during receiving valid data. Cleared to 0 when this register is read.
Remote Controller Mode: Not used.
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Publication Release Date: March 1998
Revision 0.58