W83977F Datasheet, PDF (71/181 Pages) Winbond – PLUG & PLAY 1.0A COMPLIANT

W83977F/ W83977AF
PRELIMINARY
Bit 2:
Bit 1, 0:
MIR, FIR modes:
EN_DMA - Enable DMA
Enable DMA function for transmitting or receiving. Before using this, the DMA channel
should be selected first. If only RX DMA channel is set and TX DMA channel is disabled,
then the single DMA channel is used. In the single channel system, the bit of D_CHSW
(DMA channel swap, in Set 2.Reg2.Bit3) will determine if it is RX_DMA or TX_DMA
channel.
Other modes: Not used.
RTS, DTR
Functional definitions is the same as in legacy IR mode.
4.2.6 Set0.Reg5 - IR Status Register (USR)
Mode
B7
B6
B5
Legacy IR RFEI
Advanced IR LB_INFR
Reset Value
0
TSRE
TSRE
0
TBRE
TBRE
0
B4
B3
B2
SBD
NSER PBER
MX_LEX PHY_ERR CRC_ERR
0
0
0
B1
OER
OER
0
B0
RDR
RDR
0
Legacy IR Register: These registers are defined the same as previous description.
Advanced IR Register:
Bit 7: MIR, FIR Modes:
LB_INFR - Last Byte In Frame End
Set to 1 when last byte of a frame is in the bottom of FIFO. This bit separates one frame
from another when RX FIFO has more than one frame.
Bit 6, 5: Same as legacy IR description.
Bit 4: MIR, FIR modes:
MX_LEX - Maximum Frame Length Exceed
Set to 1 when the length of a frame from the receiver has exceeded the programmed
frame length defined in SET4.Reg6 and Reg5. If this bit is set to 1, the receiver will not
Bit 3:
receive any data to RX FIFO.
MIR, FIR modes:
PHY_ERR - Physical Layer Error
Set to 1 when an illegal data symbol is received. The illegal data symbol is defined in
physical layer of IrDA version 1.1. When this bit is set to 1, the decoder of receiver will
Bit 2:
be aborted and a frame end signal is set to 1.
MIR, FIR Modes:
CRC_ERR - CRC Error
Bit 1, 0:
Set to 1 when an attached CRC is erroneous.
OER - Overrun Error, RDR - RBR Data Ready
Definitions are the same as legacy IR.
4.2.7 Set0.Reg6 - Reserved
4.2.8 Set0.Reg7 - User Defined Register (UDR/AUDR)
Mode
Bit 7
Bit 6
Bit 5
Bit 4
Legacy IR Bit 7
Advanced FLC_ACT
IR
Reset Value
0
Bit 6
UNDRN
0
Bit 5
RX_BSY/
RX_IP
0
Bit 4
LST_FE/
RX_PD
0
Bit 3
Bit 3
S_FEND
0
Bit 2
Bit 2
0
0
Bit 1
Bit 1
LB_SF
Bit 0
Bit 0
RX_TO
0
0
- 59 -
Publication Release Date: March 1998
Revision 0.58