W83977F Datasheet, PDF (107/181 Pages) Winbond – PLUG & PLAY 1.0A COMPLIANT

W83977F/ W83977AF
Time, Calendar, Alarm A, and Alarm B data Modes continued
PRELIMINARY
REGISTER FUNCTION
RANGE(DATA MODE)
EXAMPLE
LOCATION
BINARY
BCD
BINARY
BCD
Register 05h Hours Alarm A 01h-0Ch(AM) 01h-12h(AM)
08h
08h
(12-Hour Mode) 81h-8Ch(PM) 81h-92h(PM)
(24-Hour Mode) 00h-17h
00h-23h
08h
08h
Register 06h Day of Week 01h-07h
01h-07h
02h
02h
Register 07h Date of Month 01h-1Fh
01h-31h
04h
04h
Register 08h Month
01h-0Ch
01h-12h
07h
07h
Register 09h Year
00h-63h
00h-99h
61h
97h
Register 40h Century
00h-63h
Register 41h Sec. Alarm B 00h-3Bh
00h-99h
00h-59h
13h
19h
1Eh
30h
Register 42h Min. Alarm B 00h-3Bh
00h-59h
1Eh
30h
Register 43h Hours Alarm B 01h-0Ch(AM) 01h-12h(AM)
08h
08h
(12-Hour Mode) 81h-8Ch(PM) 81h-92h(PM)
(24-Hour Mode) 00h-17h
00h-23h
08h
08h
Register 44h Day of Week 01h-07h
Alarm B
01h-07h
02h
02h
Register 45h Date of Month 01h-1Fh
Alarm B
01h-31h
04h
04h
Register 46h Month Alarm B 01h-0Ch
01h-12h
07h
07h
Register 47h Year Alarm B 00h-63h
00h-99h
61h
97h
Register 48h Century Alarm 00h-63h
B
00h-99h
13h
19h
6.2 Update Cycle
The RTC executes an update cycle once per second. It is in an update cycle when RTC updates the
contents of the clock and calendar registers. In the meantime, RTC also compares each alarm byte
with corresponding timer byte and generates an alarm flag if a match or a don't care condition (0C0h)
is present in the alarm register.
The update-in-progress bit (UIP) in register A pulses high once per second. The update cycle occurs
244µS after the UIP bit goes high. This bit is cleared and the update-ended flag (UF) is set in the end
of an update cycle.
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Publication Release Date:March 1998
Revision 0.58