W83977F Datasheet, PDF (125/181 Pages) Winbond – PLUG & PLAY 1.0A COMPLIANT

8.2 Alternate I/O Functions
W83977F/ W83977AF
PRELIMINARY
W83977F/ AF provides several alternate functions which are scattered among the GP I/O ports.
Table 8.2.1 shows their assignments. Polarity bit can also be set to alter their polarity of alternate
functions.
Table 8.2.1
GP I/O PORT
GP10
GP11
GP12
GP13
GP14
GP15
GP16
GP17
GP20
GP21
GP22
GP23
GP24
GP25
ALTERNATE FUNCTION
Interrupt Steering
Interrupt Steering
Watching Dog Timer Output/IRRX input
Power LED output/ IRTX output [W83977AF only]
General Purpose Address Decoder/ Keyboard Inhibit(P17)
General Purpose Write Strobe/ 8042 P12
Watching Dog Timer Output
Power LED output
Keyboard Reset (8042 P20)
8042 P13
8042 P14
8042 P15
8042 P16
GATE A20 (8042 P21)
8.2.1 Interrupt Steering
GP10 and GP11 can be programmed to map their own interrupt channels. The selection of IRQ
channel can be done in configure registers CR70 and CR72 of logical device 7. Each interrupt
channel also has its own 1 ms debounce filter that is used to reject any noise which is equal to or less
than 1 ms wide.
8.2.2 Watch Dog Timer Output
Watch Dog Timer contains a one minutes resolution down counter, CRF2 of Logical Device 8, and
two watch Dog control registers, WDT_CTRL0 and WDT_CTRL1 of Logical Device 8. The down
counter can be programmed within the range from 1 to 255 minutes. Writing any new non-zero value
to CRF2 or reset signal coming from a Mouse interrupt or Keyboard interrupt (CRF2 also contains
non-zero value) will cause the Watch Dog Timer to reload and start to count down from the new
value. As the counter reaches zero, (1) Watch Dog Timer time-out occurs and the bit 0 of
WDT_CTRL1 will be set to logic 1; (2) Watch Dog interrupt output is asserted if the interrupt is enable
in CR72 of logical device 8; and (3) Power LED starts to toggle output if the bit 3 of WDT_CTRL0 is
enabled. WDT_CTRL1 also can be accessed through GP2 I/O base address + 1.
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Publication Release Date: March 1998
Revision 0.58