W83977F Datasheet, PDF (108/181 Pages) Winbond – PLUG & PLAY 1.0A COMPLIANT

UPDATE CYCLE TIME TABLE
UIP BIT
1
UPDATE CYCLE TIME (T_UC)
1984µS
0
-
W83977F/ W83977AF
PRELIMINARY
BEFORE UPDATE CYCLE TIME (T_BUC MIN)
-
244µS
Update Period and UIP Timing
Update Period(1 Second)
tBUC
tUC
6.3 REGISTERS
The RTC has four control/status registers. They are accessible at all times.
6.3.1 Register 0Ah
• All bits are unaffected by RESET.
• Register A is a read/write register except bit 7 (UIP is read only).
BIT
7
6
5
4
3
2
1
0
NAME
UIP
DV2
DV1
DV0
RS3
RS2
RS1
RS0
UIP : (read only)
When UIP is 1, an update cycle is in progress. The UIP is cleared in the end of an update cycle and
when the SET bit in register B is 1.
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Publication Release Date: January 1997
Revision 0.50