W83977F Datasheet, PDF (72/181 Pages) Winbond – PLUG & PLAY 1.0A COMPLIANT

W83977F/ W83977AF
Legacy IR Register:
This is a temporary register that can be accessed and defined by the user.
PRELIMINARY
Advanced IR Register:
Bit 7 MIR, FIR Modes:
FLC_ACT - Flow Control Active
Set to 1 when the flow control occurs. Cleared to 0 when this register is read. Note that
Bit 6
this will be affected by Set5.Reg2 which controls the SIR mode switches to MIR/FIR
mode or MIR/FIR mode operated in DMA function switches to SIR mode.
MIR, FIR Modes:
UNDRN - Underrun
Set to 1 when transmitter is empty and S_FEND (bit 3 of this register) is not set in PIO
Bit 5
mode or no TC (Terminal Count) in DMA mode. Cleared to 0 after a write to 1.
MIR, FIR Modes:
RX_BSY - Receiver Busy
Set to 1 when receiver is busy or active in process.
Remote IR mode:
RX_IP - Receiver in Process
Bit 4:
Set to 1 when receiver is in process.
MIR, FIR modes:
LST_FE - Lost Frame End
Set to 1 when a frame end in a entire frame is lost. Cleared to 0 when this register is
read.
Remote IR Modes:
RX_PD - Receiver Pulse Detected
Set to 1 when one or more remote pulses are detected. Cleared to 0 when this register is
Bit 3
read.
MIR, FIR Modes:
S_FEND - Set a Frame End
Set to 1 when trying to terminate the frame, that is, the procedure of PIO command is
An Entire Frame = Write Frame Data (First) + Write S_FEND (Last)
Bit 2:
Bit 1:
Bit 0:
This bit should be set to 1, if use in PIO mode, to avoid transmitter underrun. Note that
setting S_FEND to 1 is equivalent to TC (Terminal Count) in DMA mode. Therefore, this
bit should be set to 0 in DMA mode.
Reserved.
MIR, FIR Modes:
LB_SF - Last Byte Stay in FIFO
A 1 in this bit indicates one or more frame ends still stay in receiver FIFO.
MIR, FIR, Remote IR Modes:
RX_TO - Receiver FIFO or Frame Status FIFO time-out
Set to 1 when receiver FIFO or frame status FIFO time-out occurs
4.3 Set1 - Legacy Baud Rate Divisor Register
Address Offset
0
1
2
3
4
5
6
7
Register Name
Register Description
BLL
Baud Rate Divisor Latch (Low Byte)
BHL
ISR/UFR
UCR/SSR
Baud Rate Divisor Latch (High Byte)
Interrupt Status or IR FIFO Control Register
IR Control or Sets Select Register
HCR
Handshake Control Register
USR
HSR
UDR/ESCR
IR Status Register
Handshake Status Register
User Defined Register
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Publication Release Date: March 1998
Revision 0.58