W83977F Datasheet, PDF (76/181 Pages) Winbond – PLUG & PLAY 1.0A COMPLIANT

W83977F/ W83977AF
4.4.5 Reg6 - Transmitter FIFO Depth (TXFDTH) (Read Only)
PRELIMINARY
Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Advanced IR
0
Reset Value
0
0
TXFD5 TXFD4 TXFD3 TXFD2 TXFD1 TXFD1
0
0
0
0
0
0
0
Bit 7~6:
Bit 5~0:
Reserved, Read 0.
Reading these bits returns the current transmitter FIFO depth, that is, the number of
bytes left in the transmitter FIFO.
4.4.6 Reg7 - Receiver FIFO Depth (RXFDTH) (Read Only)
Mode
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Advanced IR
0
Reset Value
0
0
RXFD5 RXFD4 RXFD3
0
0
0
0
Bit 2
RXFD2
0
Bit 1
RXFD1
0
Bit 0
RXFD1
0
Bit 7~6:
Bit 5~0:
Reserved, Read 0.
Reading these bits returns the current receiver FIFO depth, that is, the number of bytes
left in the receiver FIFO.
4.5 Set3 - Version ID and Mapped Control Registers
Address Offset
0
1
2
3
4
5
6
7
Register Name
Register Description
AUID
MP_UCR
Advanced IR ID
Mapped IR Control Register
MP_UFR Mapped IR FIFO Control Register
SSR
Sets Select Register
Reversed
-
Reserved
-
Reserved
-
Reserved
-
4.5.1 Reg0 - Advanced IR ID (AUID)
This register is read only. It stores advanced IR version ID. Reading it returns 1XH.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SSR
Default Value
SSR7
0
SSR6
0
SSR5
0
SSR4
1
SSR3
X
SSR2
X
SRR1
X
Bit 0
SRR0
X
4.5.2 Reg1 - Mapped IR Control Register (MP_UCR)
This register is read only. Reading this register returns IR Control Register value of Set 0.
Reg.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
SSR
Default Value
SSR7
0
SSR6
0
SSR5
0
SSR4
0
SSR3
0
SSR2
0
SRR1
0
Bit 0
SRR0
0
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Publication Release Date: March 1998
Revision 0.58