W83L517D_05 Datasheet, PDF (68/133 Pages) Winbond – LPC I/O for Notebook

W83L517D/W83L517D-F
8.3.2 Set1.Reg 2~7
These registers are defined the same as Set 0 registers.
8.4 Set2 - Interrupt Status or IR FIFO Control Register (ISR/UFR)
These registers are only used in advanced modes.
Address Offset Register Name
Register Description
0
ABLL
Advanced Baud Rate Divisor Latch (Low Byte)
1
ABHL
Advanced Baud Rate Divisor Latch (High Byte)
2
ADCR1
Advanced IR Control Register 1
3
SSR
Sets Select Register
4
ADCR2
Advanced IR Control Register 2
5
Reserved -
6
TXFDTH
Transmitter FIFO Depth
7
RXFDTH
Receiver FIFO Depth
8.4.1 Reg0, 1 - Advanced Baud Rate Divisor Latch (ABLL/ABHL)
These two registers are the same as legacy IR baud rate divisor latch in SET 1.Reg0~1. In advanced
SIR/ASK-IR mode, the user should program these registers to set baud rate. This is to prevent
backward operations from occurring.
8.4.2 Reg2 - Advanced IR Control Register 1 (ADCR1)
MODE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Advanced IR BR_OUT
-
EN_LOU
T
ALOOP D_CHSW DMATHL
DMA_F
ADV_SL
Reset Value
0
0
0
0
0
0
0
0
Bit 7:
Bit 6:
Bit 5:
BR_OUT - Baud Rate Clock Output
When written to 1, the programmed baud rate clock will be output to DTR pin. This bit is
only used to test baud rate divisor.
Reserved, write 0.
EN_LOUT - Enable Loopback Output
A write to 1 will enable transmitter to output data to IRTX pin when loopback operation
occurs. Internal data can be verified through an output pin by setting this bit.
- 68 -