W83L517D_05 Datasheet, PDF (52/133 Pages) Winbond – LPC I/O for Notebook

W83L517D/W83L517D-F
7.2.6 Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
7 65 4 3 21 0
00
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
Bit 7, 6:
These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4:
These two bits are always logic 0.
Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-
out interrupt is pending.
Bit 2, 1:
below.
These two bits identify the priority level of the pending interrupt, as shown in the table
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
this bit will be set to a logical 0.
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