W83L517D_05 Datasheet, PDF (59/133 Pages) Winbond – LPC I/O for Notebook

W83L517D/W83L517D-F
8.2.3 Set0.Reg2 - Interrupt Status Register/IR FIFO Control Register (ISR/UFR)
Interrupt Status Register (Read Only)
MODE
B7
B6
B5
B4
B3
B2
B1
B0
Legacy IR FIFO Enable FIFO Enable 0
0
IID2
IID1
IID0
IP
Advanced IR TMR_I
FSF_I
TXTH_I DMA_I HS_I
USR_I/
FEND_I
TXEMP_I RXTH_I
Reset Value
0
0
1
0
0
0
1
0
Legacy IR:
This register reflects the Legacy IR interrupt status, which is encoded by different interrupt sources
into 3 bits.
Bit 7, 6:
These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4:
These two bits are always logical 0.
Bit 3: When not in FIFO mode, this bit is always 0. In FIFO mode, both bit 3 and 2 are set to logical 1
when a time-out interrupt is pending.
Bit 2, 1:
below.
These bits identify the priority level of the pending interrupt, as shown in the table
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
this bit will be set to logical 0.
TABLE: INTERRUPT CONTROL FUNCTION
ISR
INTERRUPT SET AND FUNCTION
Bit Bit Bit Bit Interrupt Interrupt
3 2 1 0 priority
Type
Interrupt Source
Clear Interrupt
00 0 1
-
-
No Interrupt pending
-
01 1 0
First
IR Receive ^{1. OER = 1 2. PBER =1}
Status
3. NSER = 1 4. SBD = 1
Read USR
1. RBR data ready
1. Read RBR
01
0
0
Second
RBR Data
Ready
2. FIFO interrupt active
level reached
2. Read RBR until
FIFO data under
active level
Data present in RX FIFO
11
0
0
Second
FIFO Data
Time-out
for 4 characters period of
time since last access of
RX FIFO.
Read RBR
0 0 1 0 Third TBR Empty
TBR empty
1. Write data into
TBR
2. Read ISR (if
priority is third)
** Bit 3 of ISR is enabled when bit 0 of UFR is a logical 1.
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Publication Release Date: May 23, 2005
Revision 1.0