W83L517D_05 Datasheet, PDF (21/133 Pages) Winbond – LPC I/O for Notebook

W83L517D/W83L517D-F
5. LPC (LOW PIN COUNT) INTERFACE
LPC interface is to replace ISA interface serving as a bus interface between host (chip-set) and
peripheral (Winbond I/O). Data transfer on the LPC bus are serialized over a 4 bit bus. The general
characteristics of the interface implemented in Winbond LPC I/O are:
• One control line, namely LFRAME#, which is used by the host to start or stop transfers. No
peripherals drive this signal.
• The LAD[3:0] bus, which communicates information serially. The information conveyed are cycle
type, cycle direction, chip selection, address, data, and wait states.
• MR (master reset) of Winbond ISA I/O is replaced with a active low reset signal, namely
LRESET#, in Winbond LPC I/O.
• An additional 33 MHz PCI clock is needed in Winbond LPC I/O for synchronization.
• DMA requests are issued through LDRQ#.
• Interrupt requests are issued through SERIRQ.
• Power management events are issued through PME#.
Comparing to its ISA counterpart, LPC implementation saves up to 40 pin counts free for integrating
more devices on a single chip.
The transition from ISA to LPC is transparent in terms of software which means no BIOS or device
driver update is needed except chip-specific configuration.
6. FDC FUNCTIONAL DESCRIPTION
6.1 W83L517D FDC
The floppy disk controller of the W8369L517D integrates all of the logic required for floppy disk
control. The FDC implements a PC/AT or PS/2 solution. All programmable options default to
compatible values. The FIFO provides better system performance in multi-master systems. The
digital data separator supports up to 2 M bits/sec data rate.
The FDC includes the following blocks: AT interface, Precompensation, Data Rate Selection, Digital
Data Separator, FIFO, and FDC Core.
6.1.1 AT interface
The interface consists of the standard asynchronous signals: _RD#, WR#, A0-A3, IRQ, DMA control,
and a data bus. The address lines select between the configuration registers, the FIFO and
control/status registers. This interface can be switched between PC/AT, Model 30, or PS/2 normal
modes. The PS/2 register sets are a superset of the registers found in a PC/AT.
6.1.2 FIFO (Data)
The FIFO is 16 bytes in size and has programmable threshold values. All command parameter
information and disk data transfers go through the FIFO. Data transfers are governed by the RQM and
DIO bits in the Main Status Register.
The FIFO defaults to disabled mode after any form of reset. This maintains PC/AT hardware
compatibility. The default values can be changed through the CONFIGURE command. The advantage
of the FIFO is that it allows the system a larger DMA latency without causing disk errors. The following
tables give several examples of the delays with a FIFO. The data are based upon the following
formula:
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Publication Release Date: May 23, 2005
Revision 1.0