W83L517D_05 Datasheet, PDF (46/133 Pages) Winbond – LPC I/O for Notebook

W83L517D/W83L517D-F
Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary
format) from the divisor latches of the baudrate generator during a read or write operation. When this
bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt Control
Register can be accessed.
Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is
affected by this bit; the transmitter is not affected.
Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1,
(1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check.
(2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check.
TABLE 7-1 UART Register Bit Map
BIT NUMBER
REGISTER
ADDRESS BASE
0
1
2
3
4
+0
Receiver
RX Data
Buffer
BDLAB _Register
RBR
Bit 0
= 0 _{(Read Only)}
RX Data
Bit 1
RX Data RX Data
Bit 2
Bit 3
RX
Data
Bit 4
5
6
7
RX
Data
Bit 5
RX Data RX Data
Bit 6
Bit 7
+ 0 ^Transmitter
Buffer
BDLAB _Register
= 0 _{(Write Only)}
TBR
TX Data
Bit 0
TX Data
Bit 1
TX Data TX Data
Bit 2
Bit 3
TX
Data
Bit 4
TX
Data
Bit 5
TX Data TX Data
Bit 6
Bit 7
+1
BDLAB
=0
Interrupt
Control
Register
ICR
RBR
Data
Ready
Interrupt
Enable
(ERDRI)
TBR
Empty
Interrupt
Enable
(ETBREI)
USR
HSR
Interrupt Interrupt
Enable Enable
(EUSRI) (EHSRI)
0
0
0
0
+2
Interrupt
Status
Register
ISR
(Read Only)
"0" if
Interrupt
Pending
Interrupt
Status
Bit (0)
Interrupt Interrupt
Status Status
Bit (1) Bit (2)**
0
FIFOs FIFOs
0 Enabled Enabled
**
**
UART FIFO
+2
Control
Register
UFR
FIFO
Enable
(Write Only)
RCVR
FIFO
Reset
XMIT
FIFO
Reset
DMA
Mode
Select
Reserved Reversed
RX
Interrupt
Active
Level
(LSB)
RX
Interrupt
Active
Level
(MSB)
+3
UART
Control
Register
UCR
Data
Length
Select
Bit 0
(DLS0)
Data
Length
Select
Bit 1
(DLS1)
Multiple
Stop Bits
Enable
(MSBE)
Parity
Bit
Enable
(PBE)
Even
Parity
Enable
Parity
Bit
Fixed
Enable
(EPE) _PBFE)
Set
Silence
Enable
(SSE)
Baudrate
Divisor
Latch
Access
Bit
(BDLAB)
+4
Handshake
Control
Register
HCR
Data
Terminal
Ready
(DTR)
Request
to
Send
(RTS)
Loopback
RI
Input
IRQ
Enable
Internal
Loopba
ck
Enable
0
0
0
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