W83L517D_05 Datasheet, PDF (67/133 Pages) Winbond – LPC I/O for Notebook

W83L517D/W83L517D-F
Bit 3
Bit 2:
Bit 1:
Bit 0:
MIR, FIR Modes:
S_FEND - Set a Frame End
Set to 1 when trying to terminate the frame, that is, the procedure od PIO command is
An Entire Frame = Write Frame Data (First) + Write S_FEND (Last)
This bit should be set to 1, if used in PIO mode, to avoid transmitter underrun. Note that
setting S_FEND to 1 is equivalent to TC (Terminal Count) in DMA mode. Therefore, this
bit should be set to 0 in DMA mode.
Reserved.
MIR, FIR Modes:
LB_SF - Last Byte Stay in FIFO
A 1 in this bit indicates one or more frame ends remain in receiver FIFO.
MIR, FIR, Remote IR Modes:
RX_TO - Receiver FIFO or Frame Status FIFO time-out
Set to 1 when receiver FIFO or frame status FIFO time-out occurs
8.3 Set1 - Legacy Baud Rate Divisor Register
ADDRESS OFFSET REGISTER NAME
REGISTER DESCRIPTION
0
BLL
Baud Rate Divisor Latch (Low Byte)
1
BHL
Baud Rate Divisor Latch (High Byte)
2
ISR/UFR
Interrupt Status or IR FIFO Control Register
3
UCR/SSR
IR Control or Sets Select Register
4
HCR
Handshake Control Register
5
USR
IR Status Register
6
HSR
Handshake Status Register
7
UDR/ESCR
User Defined Register
8.3.1 Set1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL)
These two registers of BLL and BHL are baud rate divisor latch in the legacy SIR/ASK-IR mode.
Accessing these registers in Advanced IR mode will cause backward operation, that is, UART will fall
back to legacy SIR mode and clear some register values as shown in the following table.
SET & REGISTER ADVANCED MODE
DIS_BACK=×
LEGACY MODE
DIS_BACK=0
Set 0.Reg 4
Bit 7~5
-
Set 2.Reg 2
Bit 0, 5, 7
Bit 5, 7
Set 4.Reg 3
Bit 2, 3
-
Note that DIS_BACK=1 (Disable Backward operation) in legacy SIR/ASK-IR mode will not affect any register which is
meaningful in legacy SIR/ASK-IR.
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Publication Release Date: May 23, 2005
Revision 1.0