W83L517D_05 Datasheet, PDF (2/133 Pages) Winbond – LPC I/O for Notebook

W83L517D/W83L517D-F
Table of Contents-
1. GENERAL DESCRIPTION .............................................................................................................. 6
2. FEATURES...................................................................................................................................... 7
3. PIN CONFIGURATION FOR W83L517D........................................................................................ 9
4. PIN DESCRIPTION ....................................................................................................................... 10
4.1 LPC Interface....................................................................................................................... 10
4.2 FDC Interface ...................................................................................................................... 11
4.3 Multi-Mode Parallel Port ...................................................................................................... 12
4.4 Serial Port Interface and Infrared Port ................................................................................ 17
4.5 KBC and FLASH ROM Interface ......................................................................................... 19
4.6 POWER PINS...................................................................................................................... 20
5. LPC (LOW PIN COUNT) INTERFACE.......................................................................................... 21
6. FDC FUNCTIONAL DESCRIPTION.............................................................................................. 21
6.1 W83L517D FDC .................................................................................................................. 21
6.1.1 AT interface ..........................................................................................................................21
6.1.2 FIFO (Data) ..........................................................................................................................21
6.1.3 Data Separator .....................................................................................................................22
6.1.4 Write Precompensation ........................................................................................................23
6.1.5 Perpendicular Recording Mode ............................................................................................23
6.1.6 FDC Core .............................................................................................................................23
6.1.7 FDC Commands...................................................................................................................23
6.2 Register Descriptions .......................................................................................................... 34
6.2.1 Status Register A (SA Register) (Read base address + 0)...................................................34
6.2.2 Status Register B (SB Register) (Read base address + 1)...................................................36
6.2.3 Digital Output Register (DO Register) (Write base address + 2) ..........................................38
6.2.4 Tape Drive Register (TD Register) (Read base address + 3)...............................................38
6.2.5 Main Status Register (MS Register) (Read base address + 4).............................................39
6.2.6 Data Rate Register (DR Register) (Write base address + 4) ................................................39
6.2.7 FIFO Register (R/W base address + 5) ................................................................................41
6.2.8 Digital Input Register (DI Register) (Read base address + 7)...............................................43
6.2.9 Configuration Control Register (CC Register) (Write base address + 7) ..............................44
7. UART PORT .................................................................................................................................. 45
7.1 Universal Asynchronous Receiver/Transmitter (UART A) .................................................. 45
7.2 Register Address................................................................................................................. 45
7.2.1 UART Control Register (UCR) (Read/Write) ........................................................................45
7.2.2 UART Status Register (USR) (Read/Write) ..........................................................................48
7.2.3 Handshake Control Register (HCR) (Read/Write) ................................................................49
7.2.4 Handshake Status Register (HSR) (Read/Write)..................................................................50
7.2.5 UART FIFO Control Register (UFR) (Write only)..................................................................51
7.2.6 Interrupt Status Register (ISR) (Read only) ..........................................................................52
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