W83L517D_05 Datasheet, PDF (57/133 Pages) Winbond – LPC I/O for Notebook

W83L517D/W83L517D-F
8.2 Set0-Legacy/Advanced IR Control and Status Registers
ADDRESS
OFFSET
REGISTER
NAME
REGISTER DESCRIPTION
0
RBR/TBR Receiver/Transmitter Buffer Registers
1
ICR
Interrupt Control Register
2
ISR/UFR Interrupt Status or IR FIFO Control Register
3
UCR/SSR IR Control or Sets Select Register
4
HCR
Handshake Control Register
5
USR
IR Status Register
6
HSR
Handshake Status Register
7
UDR/ESCR User Defined Register
8.2.1 Set0.Reg0 - Receiver/Transmitter Buffer Registers (RBR/TBR) (Read/Write)
Receiver Buffer Register is read only and Transmitter Buffer Register is write only. When operating in
the PIO mode, the port is used to Receive/Transmit 8-bit data.
When function as a legacy IR, this port only supports PIO mode. If set in the advanced IR mode and
configured as MIR/FIR/Remote IR, this port can support DMA transmission. Two DMA channels can
be used simultaneously, one for TX DMA and the other for RX DMA. Therefore, single DMA channel
is also supported when the bit of D_CHSW (DMA Channel Swap, in Set2.Reg2.Bit3) is set and the
TX/RX DMA channel is swapped. Note that two DMA channels can be defined in configure register
CR2A which selects DMA channel or disables DMA channel. If only RX DMA channel is enabled
while TX DMA channel is disabled, then the single DMA channel will be selected.
8.2.2 Set0.Reg1 - Interrupt Control Register (ICR)
MODE
B7
B6
B5
B4
B3
Legacy IR
0
0
0
0
0
Advanced IR ETMRI EFSFI ETXTHI EDMAI 0
B2
EUSRI
EUSRI/
TXURI
B1
B0
ETBREI ERDRI
ETBREI ERBRI
The advanced IR functions including Advanced SIR/ASK-IR, MIR, FIR, or Remote IR are described
below.
Bit 7:
Legacy IR Mode:
Not used. A read will return 0.
Advanced IR Mode:
ETMRI - Enable Timer Interrupt
A write to 1 will enable timer interrupt.
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Publication Release Date: May 23, 2005
Revision 1.0