W83L517D_05 Datasheet, PDF (48/133 Pages) Winbond – LPC I/O for Notebook

W83L517D/W83L517D-F
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TABLE 7-2 WORD LENGTH DEFINITION
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DATA LENGTH
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5 bits
1
6 bits
0
7 bits
1
8 bits
7.2.2 UART Status Register (USR) (Read/Write)
This 8-bit register provides information about the status of the data transfer during communication.
7654 321 0
RBR Data ready (RDR)
Overrun error (OER)
Parity bit error (PBER)
No stop bit error (NSER)
Silent byte detected (SBD)
Transmitter Buffer Register empty (TBRE)
Transmitter Shift Register empty (TSRE)
RX FIFO Error Indication (RFEI)
Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic 1
when there is at least one parity bit error, no stop bit error or silent byte detected in the FIFO. In 16550
mode, this bit is cleared by reading from the USR if there are no remaining errors left in the FIFO.
Bit 6: TSRE. In 16450 mode, when TBR and TSR are both empty, this bit will be set to a logical 1. In
16550 mode, if the transmit FIFO and TSR are both empty, it will be set to a logical 1. Other thanthese
two cases, this bit will be reset to a logical 0.
Bit 5: TBRE. In 16450 mode, when a data character is transferred from TBR to TSR, this bit will be set
to a logical 1. If ETREI of ICR is a logical 1, an interrupt will be generated to notify the CPU to write
the next data. In 16550 mode, this bit will be set to a logical 1 when the transmit FIFO is empty. It will
be reset to a logical 0 when the CPU writes data into TBR or FIFO.
Bit 4: SBD. This bit is set to a logical 1 to indicate that received data are kept in silent state for a full
word time, including start bit, data bits, parity bit, and stop bits. In 16550 mode, it indicates the same
condition for the data on top of the FIFO. When the CPU reads USR, it will clear this bit to a logical 0.
Bit 3: NSER. This bit is set to a logical 1 to indicate that the received data have no stop bit. In 16550
mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads USR, it
will clear this bit to a logical 0.
Bit 2: PBER. This bit is set to a logical 1 to indicate that the parity bit of received data is wrong. In
16550 mode, it indicates the same condition for the data on top of the FIFO. When the CPU reads
USR, it will clear this bit to a logical 0.
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