W83L517D_05 Datasheet, PDF (65/133 Pages) Winbond – LPC I/O for Notebook

W83L517D/W83L517D-F
8.2.6 Set0.Reg5 - IR Status Register (USR)
MODE
B7
B6
B5
B4
B3
B2
B1
B0
Legacy IR RFEI TSRE TBRE
SBD
NSER
PBER OER RDR
Advanced IR LB_INFR TSRE TBRE MX_LEX PHY_ERR CRC_ERR OER RDR
Reset Value
0
0
0
0
0
0
0
0
Legacy IR Register: These registers are defined the same as previous description.
Advanced IR Register:
Bit 7: MIR, FIR Modes:
LB_INFR - Last Byte In Frame End
Set to 1 when last byte of a frame is in the bottom of FIFO. This bit separates one frame
from another when RX FIFO has more than one frame.
Bit 6, 5: Same as legacy IR description.
Bit 4: MIR, FIR modes:
MX_LEX - Maximum Frame Length Exceed
Set to 1 when the length of a frame from the receiver has exceeded the programmed
frame length defined in SET4.Reg6 and Reg5. If this bit is set to 1, the receiver will not
receive any data to RX FIFO.
Bit 3: MIR, FIR modes:
PHY_ERR - Physical Layer Error
Set to 1 when an illegal data symbol is received. The illegal data symbol is defined in
physical layer of IrDA version 1.1. When this bit is set to 1, the decoder of receiver will
be aborted and a frame end signal is set to 1.
Bit 2: MIR, FIR Modes:
CRC_ERR - CRC Error
Set to 1 when an attached CRC is erroneous.
Bit 1, 0: OER - Overrun Error, RDR - RBR Data Ready
Definitions are the same as legacy IR.
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Publication Release Date: May 23, 2005
Revision 1.0