W83L517D_05 Datasheet, PDF (61/133 Pages) Winbond – LPC I/O for Notebook

W83L517D/W83L517D-F
MODE
Legacy IR
Advanced IR
Reset Value
BIT 7
RXFTL1
(MSB)
RXFTL1
(MSB)
0
IR FIFO Control Register (UFR):
BIT 6 BIT 5 BIT 4 BIT 3 BIT 2
BIT 1
BIT 0
RXFTL0
(LSB)
0
0
0 TXF_RST RXF_RST EN_FIFO
RXFTL0 TXFTL1 TXFTL0
(LSB) (MSB) (LSB)
0 TXF_RST RXF_RST EN_FIFO
0
0
0
0
0
0
0
Legacy IR:
This register is used to control FIFO functions of the IR.
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
the interrupt active level is set as 4 bytes and there are more than 4 data characters in the receiver
FIFO, the interrupt will be activated to notify CPU to read the data from FIFO.
BIT 7
0
0
1
1
BIT 6
0
1
0
1
TABLE: FIFO TRIGGER LEVEL
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
01
04
08
14
Bit 4, 5:
Reserved
Bit 3:
When this bit is programmed to logic 1, the DMA mode will change from mode 0 to
mode 1 if UFR bit 0 = 1.
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to its initial state. This bit will be
cleared to logical 0 by itself after being set to logical 1.
Bit 1: Setting this bit to logical 1 resets the RX FIFO counter logic to its initial state. This bit will be
cleared to a logical 0 by itself after being set to logical 1.
Bit 0: This bit enables the 16550 (FIFO) mode of the IR. This bit should be set to logical 1 before
other bits of UFR can be programmed.
Advanced IR:
BIT 7, 6:
RXFTL1, 0 – RECEIVER FIFO THRESHOLD LEVEL
Its definition is the same as Legacy IR. RXTH_I becomes 1 when the Receiver FIFO
Threshold Level is equal to or larger than the defined value shown as follow.
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Publication Release Date: May 23, 2005
Revision 1.0