W83L517D_05 Datasheet, PDF (53/133 Pages) Winbond – LPC I/O for Notebook

W83L517D/W83L517D-F
TABLE 7-4 INTERRUPT CONTROL FUNCTION
ISR
INTERRUPT SET AND FUNCTION
Bit Bit Bit Bit Interrupt
3 2 1 0 priority
Interrupt
Type
Interrupt Source
Clear Interrupt
0001
-
0 1 1 0 First
-
UART
Receive
Status
No Interrupt pending
1. OER = 1 2. PBER =1
3. NSER = 1 4. SBD = 1
-
Read USR
0
1
0
0 Second
RBR Data
Ready
1. RBR data ready
2. FIFO interrupt active
level reached
1. Read RBR
2. Read RBR until
FIFO data under active
level
Data present in RX FIFO
1
1
0
0 Second
FIFO Data for 4 characters period of
Timeout time since last access of
RX FIFO.
Read RBR
0 0 1 0 Third TBR Empty
TBR empty
1. Write data into TBR
2. Read ISR (if priority
is third)
0
0
0
0
Fourth
Handshake ^{1. TCTS = 1 2. TDSR = 1}
status _{3. FERI = 1 4. TDCD = 1}
Read HSR
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
7.2.7 Interrupt Control Register (ICR) (Read/Write)
This 8-bit register allows the five types of controller interrupts to activate the interrupt output signal
separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt
Control Register (ICR). A selected interrupt can be enabled by setting the appropriate bits of this
register to a logical 1.
7 65 4 3 2 1 0
0 0 00
RBR data ready interrupt enable (ERDRI)
TBR empty interrupt enable (ETBREI)
UART receive status interrupt enable (EUSRI)
Handshake status interrupt enable (EHSRI)
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Publication Release Date: May 23, 2005
Revision 1.0