W83L517D_05 Datasheet, PDF (22/133 Pages) Winbond – LPC I/O for Notebook

W83L517D/W83L517D-F
THRESHOLD # × (1/DATA/RATE) *8 - 1.5 μS = DELAY
FIFO THRESHOLD
1 Byte
2 Byte
8 Byte
15 Byte
MAXIMUM DELAY TO SERVICING AT 500K BPS
Data Rate
1 × 16 μS - 1.5 μS = 14.5 μS
2 × 16 μS - 1.5 μS = 30.5 μS
8 × 16 μS - 1.5 μS = 6.5 μS
15 × 16 μS - 1.5 μS = 238.5 μS
FIFO THRESHOLD
1 Byte
2 Byte
8 Byte
15 Byte
MAXIMUM DELAY TO SERVICING AT 1M BPS
Data Rate
1 × 8 μS - 1.5 μS = 6.5 μS
2 × 8 μS - 1.5 μS = 14.5 μS
8 × 8 μS - 1.5 μS = 62.5 μS
15 × 8 μS - 1.5 μS = 118.5 μS
At the start of a command the FIFO is always disabled and command parameters must be sent based
upon the RQM and DIO bit settings in the main status register. When the FDC enters the command
execution phase, it clears the FIFO of any data to ensure that invalid data are not transferred.
An overrun and underrun will terminate the current command and the data transfer. Disk writes will
complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to
remove the remaining data so that the result phase may be entered.
DMA transfers are enabled with the SPECIFY command and are initiated by the FDC by activating the
DRQ pin during a data transfer command. The FIFO is enabled directly by asserting DACK# and
addresses need not be valid.
Note that if the DMA controller is programmed to function in verify mode a pseudo read is performed
by the FDC based only on DACK#. This mode is only available when the FDC has been configured
into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled the above
operation is performed by using the new VERIFY command. No DMA operation is needed.
6.1.3 Data Separator
The function of the data separator is to lock onto the incoming serial read data. When a lock is
achieved the serial front end logic of the chip is provided with a clock which is synchronized to the
read data. The synchronized clock, called the Data Window, is used to internally sample the serial
data portion of the bit cell, and the alternate state samples the clock portion. Serial to parallel
conversion logic separates the read data into clock and data bytes.
The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking.
The DDS circuit cycles once every 12 clock cycles ideally. Any data pulse input will be synchronized
and then adjusted by immediate error adjustment. The control logic will generate RDD and RWD for
every pulse input. During any cycle where no data pulse is present, the DDS cycles are based on
speed. A digital integrator is used to keep track of the speed changes in the input data stream.
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