W83L517D_05 Datasheet, PDF (66/133 Pages) Winbond – LPC I/O for Notebook

W83L517D/W83L517D-F
8.2.7 Set0.Reg6 - Reserved
Set0.Reg7 - User Defined Register (UDR/AUDR)
MODE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
Legacy IR Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Advanced
IR
FLC_ACT
UNDRN
RX_BSY/
RX_IP
LST_FE/
RX_PD
S_FEND
0
Reset Value
0
0
0
0
0
0
BIT 1
Bit 1
BIT 0
Bit 0
LB_SF RX_TO
0
0
Legacy IR Register:
This is a temporary register that can be accessed and defined by the user.
Advanced IR Register:
Bit 7 MIR, FIR Modes:
FLC_ACT - Flow Control Active
Set to 1 when the flow control occurs. Cleared to 0 when this register is read. Note that
this will be affected by Set5.Reg2 which controls the SIR mode switches to MIR/FIR
mode or MIR/FIR mode operated in DMA function switches to SIR mode.
Bit 6 MIR, FIR Modes:
UNDRN - Underrun
Set to 1 when transmitter is empty and S_FEND (bit 3 of this register) is not set in PIO
mode or no TC (Terminal Count) in DMA mode. Cleared to 0 after a write to 1.
Bit 5 MIR, FIR Modes:
RX_BSY - Receiver Busy
Set to 1 when receiver is busy or active in process.
Remote IR mode:
RX_IP - Receiver in Process
Set to 1 when receiver is in process.
Bit 4: MIR, FIR modes:
LST_FE - Lost Frame End
Set to 1 when a frame end in a entire frame is lost. Cleared to 0 when this register is
read.
Remote IR Modes:
RX_PD - Receiver Pulse Detected
Set to 1 when one or more remote pulses are detected. Cleared to 0 when this register
is read.
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